Senior Device Integration Engineer (Yield & SRAM)

Samsung Electronics America; Austin (TX); Vor Ort; USD 131.000 - 175.000; Vollzeit

Benefits dieser Stelle

Medical, dental, and vision insurance

Life insurance and 401(k) matching

Onsite café(s) and workout facilities

Paid maternity and paternity leave

Paid time off plus holidays

Wellness incentives

Zusammenfassung

Samsung Austin Semiconductor seeks a Device Integration Engineer to optimize transistor performance and improve parametric yield during mass production and 14nm derivative tech. You will collaborate with Module Integration and Process Architecture to define targeting conditions and understand SRAM behavior across designs and tests.

The role demands deep device physics know-how, experience with ET, yield analysis, and cross-functional problem solving in a high-volume foundry environment.

Qualifikationen

• Bachelor level degree in Electrical/Computer/Chemical/Material Science or related field.
• MS or PhD preferred; 8+ years in semiconductor industry required.
• Experience with device physics and yield/ET interactions.

Aufgaben

• Target transistor performance to meet ET trends and product specs.
• Analyze inline metrology and ET data for yield impact.
• Own Parametric Yield and WAT management for accounts/products.
• Run experiments to optimize transistor performance and variability.
• Lead cross-functional teams to resolve yield or reliability issues.
• Support process units with device impact assessment.
• Perform SRAM performance analysis across corners and temps.

Kenntnisse

Device physics

Electrical test

Parametric yield analysis

Data mining

DOE & SPC

JR/Spotfire

SRAM performance analysis

SPICE modeling

Ausbildung

Bachelor's in Electrical/Computer/Material

Master's or PhD a plus

Tools

JMP

Spotfire

SPICE

Jobbeschreibung

Samsung Austin Semiconductor seeks a Device Integration Engineer to optimize transistor performance and improve parametric yield during mass production and 14nm derivative tech. You will collaborate with Module Integration and Process Architecture to define targeting conditions and understand SRAM behavior across designs and tests.

The role demands deep device physics know-how, experience with ET, yield analysis, and cross-functional problem solving in a high-volume foundry environment.