Device Integration Engineer: Transistor Performance & Yield

Samsung Semiconductor

Austin (TX)

On-site

USD 131,000 - 175,000

Full time

7 days ago
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Benefits offered by this job

Medical/Dental/Vision insurance
Life Insurance + 401(k) matching
Onsite facilities (cafés/workout)

Job summary

Samsung Austin Semiconductor in Austin, TX is seeking a Device Integration Engineer to optimize transistor performance and maximize yield across mass production and 14nm derivatives. You will collaborate with Module Integration and Process Architecture teams to ensure device performance targets, SRAM behavior, and reliability across corners and temperatures.

The role requires a BS in engineering, 8+ years in semiconductors, experience with device characterization, DOE, SPC, SPICE, SRAM

Qualifications

  • Bachelor's degree in Engineering required; Masters/PhD a plus.
  • 8+ years semiconductor industry experience required; 10+ preferred.
  • Experience with technology, process & qualification development milestones.

Responsibilities

  • Ensure transistor ET trends align with specifications and perform root-cause analyses.
  • Analyze process interactions and ET data effects on Parametric Yield.
  • Own Parametric Yield and WAT management for accounts/products.
  • Conduct experiments to optimize transistor performance and yield.
  • Lead task forces to resolve yield, performance, or reliability issues.
  • Support unit process and integration teams evaluating device impact.
  • Conduct SRAM performance analysis across corners and temperatures.

Skills

Electrical engineering
Semiconductor industry experience
Process-ET interaction
Thin films & lithography
DOE & SPC analysis
SRAM verification
SPICE modeling
JMP/Spotfire

Education

Bachelor's degree in engineering

Tools

JMP
Spotfire

Job description

Samsung Austin Semiconductor in Austin, TX is seeking a Device Integration Engineer to optimize transistor performance and maximize yield across mass production and 14nm derivatives. You will collaborate with Module Integration and Process Architecture teams to ensure device performance targets, SRAM behavior, and reliability across corners and temperatures.

The role requires a BS in engineering, 8+ years in semiconductors, experience with device characterization, DOE, SPC, SPICE, SRAM

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