Senior Design Verification Test Engineer – EW Systems

Anduril Industries; Costa Mesa (CA); On-site; USD 191,000 - 253,000; Full time

Benefits offered by this job

Equity grants

Top-tier benefits

Job summary

Anduril Industries seeks an experienced Design Verification Test Engineer for its Electronic Warfare team to own the DVT process and drive verification for new EW products from design to production. You will collaborate with development and test engineers to set testability requirements, write test strategy, and establish pass/fail criteria early in the design cycle.

Responsibilities include leading EVT/DVT/NPI builds on production-intent hardware, triaging failures, closing test escapes, and

Qualifications

• Must have a BS in a relevant engineering field.
• 12+ years in test/verification or product engineering.
• Experience owning test strategy and plan documentation.
• RF/microwave measurement experience required.

Responsibilities

• Own the DVT process end to end, authoring test strategy and verification plans.
• Drive development and test automation to execute verification activities.
• Build and maintain Verification Cross‑Reference Matrices.
• Analyze DVT data and establish production test limits.
• Lead EVT/DVT/NPI builds on production‑intent hardware.
• Set design verification standards and mentor test engineers.

Skills

Test strategy ownership

Leadership

Verification planning

Cross-functional collaboration

Education

B.S. in Electrical Engineering/related

Tools

Spectrum Analyzers

VNAs

Signal Generators

Power Meters

Job description

Anduril Industries seeks an experienced Design Verification Test Engineer for its Electronic Warfare team to own the DVT process and drive verification for new EW products from design to production. You will collaborate with development and test engineers to set testability requirements, write test strategy, and establish pass/fail criteria early in the design cycle.

Responsibilities include leading EVT/DVT/NPI builds on production-intent hardware, triaging failures, closing test escapes, and