Senior Design Verification Engineer

MindSource; Sunnyvale (CA); On-site; USD 125,000 - 150,000; Full time

Job summary

Join a forward-thinking company as a Design Verification Engineer, where you'll play a crucial role in defining and implementing verification plans for cutting-edge technologies. This position offers the opportunity to collaborate with talented teams across various domains, ensuring the highest quality in design verification. With a strong focus on innovation, you'll leverage your extensive experience in verification methodologies and EDA tools to drive projects to success. If you're passionate about technology and eager to make a significant impact, this role is perfect for you.

Qualifications

• 10-15 years of experience in design verification.
• Hands-on experience in verification methodologies and tools.
• Experience in architecting verification infrastructure.

Responsibilities

• Define and implement IP/SoC verification plans and test benches.
• Collaborate with cross-functional teams to ensure design quality.
• Debug and resolve functional failures in design.

Skills

Verilog

SystemVerilog

C/C++

UVM methodology

Python

Perl

Shell scripting

Education

B.S or M.S in Electrical Engineering

B.S or M.S in Computer Engineering

B.S or M.S in Computer Science

Tools

EDA tools

Mercurial (Hg)

Git

SVN

Job description

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This range is provided by MindSource. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$110.00/hr - $115.00/hr

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Location: Onsite - Sunnyvale, CA (or) Austin, TX

Duration: Long-term

Type: Contract (W2/C2C)

Rate: $110-$115/hr

Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause, and resolve functional failures in the design, partnering with the Design team
• Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality

Minimum Qualifications:

• 10-15 years of experience
• B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
• Hands-on experience in Verilog, SystemVerilog, C/C++ based verification, and UVM methodology
• Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.
• Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle

Preferred Qualifications

• Experience in the development of UVM based verification environments from scratch
• Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Experience with verification of ARM/RISC-V based sub-systems or SoCs

Interested candidates please email your latest updated resume to [e-mail]

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Contract

Job function

• Job function

  Engineering, Information Technology, and Quality Assurance

• Industries

  Technology, Information and Media

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