Senior Datacenter Compute Accelerator Architect

MediaTek Research Lab Inc.; San Jose (CA); On-site; USD 211,000 - 356,000; Full time

Benefits offered by this job

Health insurance

Disability insurance

Savings plan

Company paid holidays

Sick Leave

Vacation time

Parental leave

401K

Job summary

MediaTek Research Lab Inc. in San Jose, CA, seeks a Datacenter Compute Accelerator Architect to lead the design and integration of on-chip accelerators for next-gen DC silicon.

You will define microarchitecture for uncore blocks and ensure seamless coherence with the interconnect and memory hierarchy, while coordinating with kernel and driver teams. The role focuses on maximizing latency, bandwidth, and power efficiency for datacenter workloads, including cryptography, data analytics, and AI/ML

Qualifications

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
• 8+ years of industry experience in CPU/Compute, SoC, or accelerator architecture, with a focus on datacenter, server, storage or networking silicon.
• Deep understanding of hardware acceleration algorithms for tasks like Cryptography (AES, SHA, RSA), Tensor Core, Compression, or high-speed packet processing.
• Interconnects & Memory: Strong knowledge of on-chip coherent fabrics (AMBA AXI/CHI), memory hierarchy, and caching protocols.
• Virtualization: Hardware virtualization technologies, IOMMU/SMMU, and PCIe SR-IOV/scalable IOV.
• Programming: Proficiency in C/C++ for architectural modeling and Python for data analysis.

Responsibilities

• Define the microarchitecture and write detailed specifications for tightly-coupled uncore accelerators (e.g., Crypto/Security, Compression/Decompression, DMA engines, Tensor cores, Data Analytics offloads).
• Integrate accelerator blocks into the coherent interconnect and memory subsystem.
• Partner with kernel and driver engineers to define software models, APIs, and descriptor formats.
• Ensure accelerators support cloud-native environments with virtualization and MMU integration.
• Conduct Power, Performance, and Area (PPA) analysis and model throughput/latency.
• Lead RTL implementation, verification, and silicon bring-up to match architectural intent.

Skills

C/C++

Python

Architectural modeling

Cryptography algorithms

Tensor cores

Networking/PCIe SR-IOV

AMBA/CHI interconnect

IOMMU/SMMU virtualization

Education

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science

Tools

gem5

AMBA CHI

IOMMU/SMMU tooling

Job description

MediaTek Research Lab Inc. in San Jose, CA, seeks a Datacenter Compute Accelerator Architect to lead the design and integration of on-chip accelerators for next-gen DC silicon.

You will define microarchitecture for uncore blocks and ensure seamless coherence with the interconnect and memory hierarchy, while coordinating with kernel and driver teams. The role focuses on maximizing latency, bandwidth, and power efficiency for datacenter workloads, including cryptography, data analytics, and AI/ML