Senior CPU Cache Subsystem Design Lead

Google; Mountain View (CA); On-site; USD 240,000 - 333,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google is building custom silicon solutions that power the future of its direct-to-consumer products. You’ll contribute to innovations loved by millions and help deliver hardware experiences with unmatched performance, efficiency, and integration.

In this role you will lead CPU subsystem designs from specification to productization, coordinating with architecture, software, verification, power, DFT, and physical design teams to ship high‑quality RTL.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of CPU design experience including load-store unit logic and L2/L3 caches.
• Experience leading teams for modern processor subsystems with high speed, lower power design.

Responsibilities

• Lead and manage a front-end design team working on CPU subsystems and RTL.
• Review and propose micro-architecture features with architecture, software and verification teams.
• Ensure on-schedule delivery of RTL meeting performance, power and area goals.

Skills

CPU design experience

Team leadership

Front-end quality checks

Education

Bachelor's degree in EE/CS or equivalent

Tools

RTL design

Lint

CDC/RDC

Job description

Google is building custom silicon solutions that power the future of its direct-to-consumer products. You’ll contribute to innovations loved by millions and help deliver hardware experiences with unmatched performance, efficiency, and integration.

In this role you will lead CPU subsystem designs from specification to productization, coordinating with architecture, software, verification, power, DFT, and physical design teams to ship high‑quality RTL.