CPU Cache Subsystem Senior Design Manager

Google; City of Poughkeepsie (NY); On-site; USD 240,000 - 333,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google seeks a Senior CPU Design Lead to guide front-end design teams responsible for CPU subsystems and RTL integration into next-generation SOCs.

You will collaborate across architecture, software, verification, power, DFT and physical design to optimize micro-architecture, performance and power while meeting schedules and quality targets.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including micro-architecture definition and PPA processing.
• Experience leading and managing teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsibilities

• Lead and manage a front-end design team for CPU subsystems and RTL delivery.
• Review and propose micro-architecture enhancements with cross-functional teams.
• Deliver schedules and ensure production-quality RTL on time.
• Collaborate with verification, physical design, power, and software teams on design trade-offs.

Skills

CPU design

RTL design

Team leadership

Front-end quality checks

PPA optimization

Micro-architecture

Education

Bachelor's degree in Electrical Engineering / Computer Science or equivalent

Tools

Arm ISA

Mobile CPU subsystems

SOC integration

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including micro-architecture definition and PPA processing.
• Experience leading and managing teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Preferred qualifications

• Experience with ARM instruction set architecture.
• Experience with mobile CPU subsystem.
• Experience with mobile SOC architecture/integration.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into target SOCs.

You will lead and manage a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the micro-architecture and schedule in delivering high quality RTL that meets project goals.

You will help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google.

• Lead and manage a team of design engineers working on CPU functional units, emphasizing on micro-architecture and RTL design for the next generation CPU subsystem.
• Review/propose performance enhancing micro-architecture features, and work with Software, Architect and Performance teams for trade-off studies. Communicate the pros and cons of micro-architecture enhancements.
• Deliver with plans on achieving project milestones and goals, towards a design that meets production quality on schedule.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Focus on load-store-unit and cache subsystem design and optimizations with other parts of CPU to deliver best Performance, Power, Area (PPA).

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.