Senior CMOS Backplane Test & Validation Engineer

Socket.dev; Fremont (CA); On-site; USD 159,000 - 230,000; Full time

Job summary

Google's Hardware Testing Engineering team in the R&D lab designs test equipment for prototypes and develops protocols to scale tests globally. You’ll work with design engineers to ensure hardware meets Google’s standards of quality and reliability, contributing to the Raxium display initiative in Silicon Valley.

Individual pay is determined by job-related skills, experience, and education. US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits.

Qualifications

• Bachelor’s degree or equivalent practical experience in Electrical/Computer Engineering, Physics, or related field.
• 4 years of experience with Silicon, CMOS, and IC test development.
• 3 years of experience with Silicon test hardware, software debugging, and data analysis in an R&D or manufacturing environment.

Responsibilities

• Develop, validate, optimize CMOS backplane test solutions for microLED display panels and supporting software.
• Interface with wafer-level probe cards, test equipment, and instrumentation to enable CMOS/Silicon testing and characterization.
• Identify and resolve electrical issues during wafer-level testing using oscilloscopes and other equipment.
• Collaborate with CMOS/panel test teams to define high-speed automated testing solutions and debug manufacturing plans.
• Work with Test Engineering to enhance test frameworks per Reliability Team requirements.

Skills

Electrical engineering fundamentals

Test development

Data analysis

Firmware concepts

CMOS/ASIC testing

Education

Bachelor's degree in EE/CE/CS/Physics

Master’s degree or PhD in related field

Tools

Python

SQL databases

Linux/Ubuntu

C/C++ (bare metal)

I2C/SPI

Power supplies

Spectrometer

Job description

Google's Hardware Testing Engineering team in the R&D lab designs test equipment for prototypes and develops protocols to scale tests globally. You’ll work with design engineers to ensure hardware meets Google’s standards of quality and reliability, contributing to the Raxium display initiative in Silicon Valley.

Individual pay is determined by job-related skills, experience, and education. US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits.