Senior Board Validation & Test Engineer - ICT/FCT expert

Aeva, Inc.; Mountain View (CA); On-site; USD 125,800 - 170,200; Full time

Benefits offered by this job

Medical

Dental

Vision

401k matching

Unlimited PTO

Team lunches

Job summary

Aeva, Inc. is seeking an experienced Board Validation and Test Engineer in Mountain View, CA to drive DFT for high-volume manufacturing and develop ICT/FCT tests. You will design validation platforms and lead fast bring-up for multiple product lines.

Responsibilities include debugging power, clocks and mixed-signal paths; writing test methods in Python; and collaborating with design and CM teams to optimize yield and cost. Strong schematics reading and JTAG expertise are essential.

Qualifications

• Bachelor’s degree in Electrical/Electronics Engineering or equivalent.
• 7+ years of hands-on board bring up and validation.
• DFT experience and strong practical knowledge for ICT and FCT.
• Ability to read and critique schematics and PCB layouts.
• Strong understanding of analog, digital, power, and mixed-signal systems and boundary scan (JTAG).
• Proven track record of improving yield through DFT and failure analysis.

Responsibilities

• Drive PCBA testability (DFT) from schematic and functional reviews for high-volume manufacturing.
• Develop test platforms for initial board bring up and low-volume prototype builds using Python to extract metrics.
• Define ICT and FCT requirements for high-volume manufacturing with contract manufacturers.
• Conduct yield investigations and debug power integrity, clocks, resets, boot sequences, and mixed-signal paths.
• Correlate ICT/FCT failures with schematic intent, layout, and silicon performance.
• Use scopes, logic analyzers, current probes, and thermal tools to capture elusive failures.
• Create debug playbooks, DFT guidelines, and failure isolation documentation.
• Collaborate with engineering and manufacturing to ensure timely delivery with optimum test coverage and cost.
• Document test strategies and results for internal reference and compliance.
• Provide end-to-end support from NPI to high-volume manufacturing.

Skills

DFT experience

ICT & FCT

Python programming

Schematic review

Boundary scan/JTAG

Test automation

Data analysis

Problem solving

Cross-functional teamwork

CMs experience

Education

Bachelor’s degree in Electrical/Electronics Engineering

Tools

JMP

Job description

Aeva, Inc. is seeking an experienced Board Validation and Test Engineer in Mountain View, CA to drive DFT for high-volume manufacturing and develop ICT/FCT tests. You will design validation platforms and lead fast bring-up for multiple product lines.

Responsibilities include debugging power, clocks and mixed-signal paths; writing test methods in Python; and collaborating with design and CM teams to optimize yield and cost. Strong schematics reading and JTAG expertise are essential.