Senior ASIC/SoC Verification Engineer — AI-Driven

Blue Origin; United States; Remote; USD 230,000 - 323,000; Full time

Benefits offered by this job

Medical benefits

Dental & Vision

401(k) match

Paid parental leave

Stock options

Paid time off

Job summary

Blue Origin is seeking a Senior Verification Engineer to help verify its ASIC and Networking block for the TeraWave project. You will lead verification planning, develop environments, and apply constrained-random, formal, and directed testing across IP, subsystems, and full SoC.

You’ll contribute to AI-assisted stimulus and coverage analytics in a fast-paced environment. The role emphasizes cross-disciplinary collaboration, leveraging system-level thinking, and mentoring junior engineers while

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum five years of professional experience in ASIC or SoC functional verification.
• Hands-on expertise in SystemVerilog, UVM or formal testbench development and maintenance.
• Experience with metric-driven verification for planning, assertions, and functional coverage closure.
• Experience verifying complex digital control and datapath logic, including RTL and system-level debug.

Responsibilities

• Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
• Translate design specifications into verification strategies, measurable coverage goals, and high-risk scenarios.
• Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing.
• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.
• Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.
• Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels.
• Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics.
• Review testbench architecture and debug methodology, and mentor junior engineers in verification methodology.

Skills

SystemVerilog expertise

UVM experience

Formal verification

RTL & system-level debugging

Constrained-random verification

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

SystemVerilog

UVM

Formal verification

RTL debugging

Job description

Blue Origin is seeking a Senior Verification Engineer to help verify its ASIC and Networking block for the TeraWave project. You will lead verification planning, develop environments, and apply constrained-random, formal, and directed testing across IP, subsystems, and full SoC.

You’ll contribute to AI-assisted stimulus and coverage analytics in a fast-paced environment. The role emphasizes cross-disciplinary collaboration, leveraging system-level thinking, and mentoring junior engineers while