Senior ASIC Verification Engineer - AI-Driven SoC & IP

Blue Origin; Central (TX); On-site; USD 230,000 - 323,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

Parental Leave

401(k) with match

Stock Options

Job summary

Blue Origin is seeking a Senior Verification Engineer for the ASIC & Networking team to verify a high-throughput modem, DSP beamformer, and related IPs and SoC blocks. You will define verification strategies, build environments, and drive coverage closure while integrating AI-assisted stimulus and regression triage.

Qualifications include 5+ years in ASIC/SoC verification, SystemVerilog/UVM or formal methods, and RTL debugging.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years of professional ASIC/SoC verification experience.
• Hands-on SystemVerilog/UVM or formal testbench development.
• Experience with metric-driven verification and coverage closure.
• Experience debugging RTL and system-level issues.

Responsibilities

• Own verification planning and execution from test plan to sign-off.
• Translate specs into verification strategy and coverage goals.
• Select verification methods (constrained-random, formal, directed testing).
• Develop environments, scoreboards, monitors, coverage components, and assertions.
• Drive coverage closure, CI/regression health, and sign-off readiness.

Skills

SystemVerilog

UVM

Formal verification

Constrained-random verification

RTL debugging

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Tools

CI systems

Scoreboards

AI-assisted verification

Job description

Blue Origin is seeking a Senior Verification Engineer for the ASIC & Networking team to verify a high-throughput modem, DSP beamformer, and related IPs and SoC blocks. You will define verification strategies, build environments, and drive coverage closure while integrating AI-assisted stimulus and regression triage.

Qualifications include 5+ years in ASIC/SoC verification, SystemVerilog/UVM or formal methods, and RTL debugging.