Senior ASIC & SoC Design Engineer

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Advanced Micro Devices, Inc. in Santa Clara, CA is seeking a Sr. Silicon Design Engineer to design, develop, and test electronic components and RTL for advanced ASICs.

You will oversee architecture, verification, and documentation, and help define interfaces for simulation. Responsibilities include transitioning RTL to physical designs, contributing to IC layout, and evaluating the full design flow from high-level concepts to synthesis, place and route, timing and power.

Qualifications

• Master’s degree in Computer Engineering, Electrical Engineering or related field.
• Experience with Verilog/SystemVerilog or VHDL; SOC/CPU architecture.
• Proficiency in C, C++, or Python.
• Familiarity with ASIC design tools (synthesis, simulation, equivalence checking, static timing analysis).

Responsibilities

• Research, design, develop, and test electronic components and systems for semiconductor devices.
• Oversee definition, design, verification, and documentation for ASIC development.
• Define module interfaces for simulation and deliver RTL.
• Transition RTL design to physical designs.
• Contribute to layout design of complex ICs and evaluate flow from high-level designs to synthesis, place and route, timing and power.
• Apply engineering principles to the design, development, and testing of AMD products.

Skills

Verilog/SystemVerilog

VHDL

C/C++/Python

ASIC Design

RTL Development

SOC/CPU Architecture

Education

Master’s degree in Computer Engineering or Electrical Engineering

Tools

Synthesis tools

Simulation tools

Equivalence checking

Static timing analysis

Job description

Advanced Micro Devices, Inc. in Santa Clara, CA is seeking a Sr. Silicon Design Engineer to design, develop, and test electronic components and RTL for advanced ASICs.

You will oversee architecture, verification, and documentation, and help define interfaces for simulation. Responsibilities include transitioning RTL to physical designs, contributing to IC layout, and evaluating the full design flow from high-level concepts to synthesis, place and route, timing and power.