Senior ASIC Physical Design Engineer

Johns Hopkins Applied Physics Laboratory; Laurel (MD); On-site; USD 105,000 - 290,000; Full time

Benefits offered by this job

Education assistance

Retirement contributions

Paid time off

Medical, dental, and vision insurance

Life and disability insurance

Flexible spending accounts

Training and development programs

Job summary

Johns Hopkins Applied Physics Laboratory seeks an experienced Senior Physical Design ASIC Engineer to advance miniature systems for various applications. In this role, you'll manage the digital back-end flow from synthesis to layout and perform essential physical verification.

The successful candidate will have at least 6 years of ASIC design experience, familiarity with Cadence tools, and the ability to obtain a security clearance. Enjoy a generous benefits package and a healthy work/life balance.

Qualifications

• At least 6 years of experience performing back-end ASIC design.
• Ability to obtain an Interim Secret level security clearance.
• Proficiency with Cadence ASIC design tools for back-end flow implementation.

Responsibilities

• Manage digital back-end flow from synthesis to top-level layout.
• Perform physical verification, including DRC, DRC+, MCD, and LVS.
• Debug and address back-end related RTL and gate-level issues.

Skills

Cadence ASIC design tools

Siemens Calibre physical verification tools

Back-end ASIC design

Custom physical layout in Cadence Virtuoso

Education

Associate’s degree in a technical field

Job description

Overview

Do you love building and prototyping robust electrical systems? Do you want to provide real impact on the nation’s toughest national security problems? If so, join our team at APL. The Miniature Device Technologies Group develops highly customized tools and techniques to carry out missions around the globe, working hand‑in‑hand with government sponsors to conceive and realize solutions that solve challenging problems.

We are seeking an experienced senior physical design ASIC engineer who will advance miniature systems for a wide range of applications. In this role you will be responsible for all backend flow aspects, including synthesis, floor‑planning, timing analysis, design partitioning, SCAN and BIST insertion, and physical verification checks. You will work closely with the ASIC design team to identify and address back‑end issues in RTL and gate‑level phases, explore process selection for new proposals, and perform custom physical design as needed.

Responsibilities

• Digital back‑end flow from synthesis to a completed, verified top‑level layout ready for tape‑out submission.
• Contribute to process selection for new designs and proposals.
• Floor‑plan top‑level layout of digital and mixed‑signal ASICs.
• Perform timing analysis and design partitioning.
• Insert SCAN and BIST for maximum defect coverage.
• Debug and address back‑end related RTL and gate‑level issues with digital designers.
• Perform all physical verification, including DRC, DRC+, MCD, and LVS.
• Execute custom physical layout.
• Assist with ASIC design environment enhancements and scripting.
• Drive process improvements and implement innovative solutions.
• Build and maintain strong working relationships with cross‑functional teams.
• Provide leadership and guidance to junior physical design engineers.
• Collaborate with the team to achieve project goals and objectives.
• Foster open communication and collaboration among stakeholders.

Qualifications

• Associate’s degree in a technical field or equivalent experience/education/certifications.
• Proficiency with Cadence ASIC design tools for back‑end flow implementation.
• Experience with Siemens Calibre physical verification tools.
• At least 6 years of experience performing back‑end ASIC design.
• Ability to obtain an Interim Secret level security clearance by the start date and ultimately obtain a Secret level clearance. U.S. citizenship required.

Preferred Qualifications

• Experience with custom physical layout in Cadence Virtuoso.
• Extensive knowledge of ASIC technology characterization for process selection.
• Active clearance or prior successful single‑scope background investigations.

Pay

• Minimum Rate: $105,000 annually.
• Maximum Rate: $290,000 annually.

Benefits

APL offers generous benefits, including education assistance, retirement contributions, paid time off, medical, dental, vision, life and disability insurance, flexible spending accounts, and training and development programs. Employees also enjoy a healthy work/life balance.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, disability, genetic information, veteran status, employment status, or any other characteristic protected by law. APL is committed to providing reasonable accommodation to individuals of all abilities. If you require a reasonable accommodation, please contact [e-mail].