Senior ASIC Package Design Engineer

K2 Space; Los Angeles (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Equity

Comprehensive benefits

Job summary

K2 Space is seeking a Senior ASIC Package Design Engineer in Los Angeles to lead FC-BGA and MCM package architectures for high-pin-count ASICs. You will partner with silicon, RF, and systems teams, guiding standards and engaging OSATs through qualification and ramp.

The ideal candidate has 5+ years in ASIC packaging with FC-BGA expertise, strong SI/PI and thermal know-how, and proficiency with SIWave/HFSS/ADS. This role offers a competitive package and equity.

Qualifications

• 5+ years in ASIC package design with FC-BGA focus.
• Strong substrate, SI/PI fundamentals, thermal management.
• Fluent in SI/PI tools such as SIWave, HFSS, and ADS.

Responsibilities

• Define FC-BGA and MCM architectures for high-pin-count ASICs.
• Lead trade studies on cost, PI/SI, thermal, and reliability.
• Collaborate with silicon and systems teams on interfaces.
• Manage vendor relationships with OSATs and substrate suppliers.
• Drive package design standards and qualification activities.

Skills

FC-BGA expertise

MCM knowledge

SI/PI simulation

Thermal management

Education

Bachelor’s degree in Packaging Engineering or related field

Tools

SIWave

HFSS

ADS

OSAT vendors

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

The Role

We are seeking aSeniorASICPackage Design Engineer toimplementadvanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This rolesupports the end-to-end package strategy for high-performance mixed-signal and digital SoCsfrom early architecture and trade studies through vendor engagement, qualification, and production ramp. You willcollaborate withinternal teamsfor package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

Responsibilities

• DefineASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Establish package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, andRF signalcontent.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimizedie floorplans and package interfaces.
• Supportpackage-level SI/PI strategy, includinghigh-speed digital interfaces, power delivery network (PDN) design,and decoupling strategy
• Lead thermal architecture at the package level, including lidselection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Manage relationships with external packaging vendors, substrate suppliers, and OSATs.
• Drive material selection, substrate technology choices, and assembly process optimization.

Qualifications

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 5+ years of experience in ASIC package design, with deepexpertisein FC-BGA.
• Strong understanding ofsubstrate technologies and materials,SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such asSIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies.

Nice to Have

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
• Background in high-speed digital or mixed-signal SoCs.
• Familiarity with aerospace, space, or high-reliability electronics.

Compensation and Benefits:

• Base salary range for this role is $180,000 – $260,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

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