Senior ASIC Methodology Engineer for ML Accelerators

Amazon Inc.; Seattle, Northern (WA, KY); Hybrid; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs, part of Amazon, seeks an ASIC Physical Design Methodology Engineer to develop and deploy RTL2GDS workflows for ML accelerator chips. You will optimize CAD flows, collaborate with RTL and DFT teams, and build scalable scripting solutions to improve QoR and project efficiency.

You will work across design teams on advanced nodes, applying TCL, Python, and automation to deliver robust, low-power designs for volume production in a cloud-scale environment.

Qualifications

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller).
• 7+ years of digital design in communication systems experience.
• 7+ years of full-custom analog or RF layout experience.
• 8+ years of automation frameworks for Post-Silicon Flow experience.
• 7+ years of verification in communication systems experience.
• 5+ years of UVM, C, System C, and scripting experience.
• 3+ years of emulation experience.
• Knowledge of UVM and Matlab.
• Experience with multi‑power islands and power gating.
• Experience in modem L1/L2 algorithms development and architectures.

Responsibilities

• Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes.
• Drive optimizations in CAD flows/methodologies for PPA and TAT improvements.
• Interface with RTL, PD, PD, DFT teams to improve methodologies and efficiencies.
• Troubleshoot digital tool flow usage and deploy scalable solutions.
• Create dashboards and central reports for project tracking and QoR/stats.

Skills

ASIC implementation

Synthesis

STA

Digital design

Verification

UVM

Python scripting

Emulation

C

Education

Bachelor's degree in Electrical Engineering or related field

Tools

UVM

Matlab

Python

Embedded C

Job description

Annapurna Labs, part of Amazon, seeks an ASIC Physical Design Methodology Engineer to develop and deploy RTL2GDS workflows for ML accelerator chips. You will optimize CAD flows, collaborate with RTL and DFT teams, and build scalable scripting solutions to improve QoR and project efficiency.

You will work across design teams on advanced nodes, applying TCL, Python, and automation to deliver robust, low-power designs for volume production in a cloud-scale environment.