Senior ASIC Floorplan Designer – GPUs/SoCs, Equity

NVIDIA Corporation; United States; On-site; USD 196,000 - 311,000; Full time

Job summary

NVIDIA Corporation is seeking an experienced ASIC Floorplan Engineer to design and implement leading SOCs, CPUs, and GPUs. You will influence the design from architecture through physical design, shaping floorplans to optimize cost, area, performance, and power for NVIDIA's flagship products.

You will collaborate with product managers, ASIC and physical design, and DFT teams to drive floorplan development, identify risks, and deliver high-quality silicon on schedule.

Qualifications

• MSEE/MSCE or equivalent experience in chip development.
• 10+ years of ASIC/SoC floorplan experience.
• Experience with SOC, CPU, graphics, memory and I/O sub-systems.
• Ability to multi-task across projects and resolve complex issues.
• Experience with physical design methodologies, floorplan, power/clock distribution, DFT, place and route, timing closure, and packaging.
• Strong written and verbal communications skills.
• Agentic AI workflows, Python, Perl and/or C++ experience.

Responsibilities

• From early chip definition phase partner with teams to craft floorplans optimizing cost/area/perf.
• Drive floorplan development and collaboration to optimize area, interconnect, timing.
• Develop AI workflows to improve infrastructure for chip area and speed.
• Identify risks and work with teams to implement mitigation strategies.

Skills

ASIC floorplan

SoC/CPU/GPU

multi-tasking

team collaboration

Education

MSEE/MSCE or equivalent

Tools

P&R tools

DFT tools

flow development

timing closure

Job description

NVIDIA Corporation is seeking an experienced ASIC Floorplan Engineer to design and implement leading SOCs, CPUs, and GPUs. You will influence the design from architecture through physical design, shaping floorplans to optimize cost, area, performance, and power for NVIDIA's flagship products.

You will collaborate with product managers, ASIC and physical design, and DFT teams to drive floorplan development, identify risks, and deliver high-quality silicon on schedule.