Senior DFT Engineer, Test Infrastructure, Google Cloud

Google; Sunnyvale (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Google Sunnyvale is seeking a Senior DFT Engineer, Test Infrastructure, Google Cloud, to shape AI/ML hardware acceleration. You will verify complex digital designs and drive DFT environments across design and manufacturing stages.

You will collaborate with design and verification teams to ensure robust DFT solutions for TPU architecture, enabling scalable AI workloads and reliable silicon bring-up. Proficiency in SystemVerilog and scripting is required.

Qualifications

• Bachelor's or equivalent in EE/CS or related field.
• 8+ years in DFT features, verification and validation.
• Experience with Python/Perl/TCL scripting.
• Experience with ATE platforms and SystemVerilog.
• Strong background in IPs like PLL, sensors, PMRO.

Responsibilities

• Define requirements for ATE tests and manufacturing flow.
• Generate and verify ATE patterns including HV/HTOL tests.
• Run pattern playbacks to ensure high quality patterns.
• Own pattern translations and integrate DFT verification into ASIC flow.
• Prepare silicon debug verification strategy and test readiness.

Skills

DFT verification

Python/Perl/TCL

ATE platforms

SystemVerilog

8+ years DFT experience

10 years test eng experience

SSN/Streaming Fabric

IP testing (PLL, sensors, PMRO)

PCIe/DDR/HBM testing

Education

Bachelors degree in EE/CS

Masters/PhD in EE/CS with architecture focus

Tools

Teradyne UltraFlex

Advantest

Job description

Senior DFT Engineer, Test Infrastructure, Google Cloud

Sunnyvale, CA, USA

Job Level: Mid

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with DFT features (e.g., JTAG/MBIST/ATPG/HSIO), verification, functional validation.
• Experience with one of the scripting languages: Python, Perl, or TCL.
• Experience with ATE platforms (e.g., Teradyne UltraFlex or Advantest).
• Experience with SystemVerilog.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• 10 years of experience in test engineering or product engineering.
• Experience with Scan/ATPG test development, especially with Streaming Scan Network (SSN)/Streaming Fabric techniques, or memory BIST test development and repair scheme implementation, including BISR/BIRA.
• Experience in testing Intellectual Property (IP) such as Phase-locked Loops (PLL), Process Voltage Temperature (PVT) sensors, thermal diodes, Process Monitor Ring Oscillator (PMRO), droop detector, aging sensor, and eFuse.
• Experience with PCIE, Double Data Rate (DDR) and HBM testing.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU technology that powers Google's most demanding AI/ML applications.

You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You’ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As a DFT Test Engineer, you will work closely with various teams within the design process and with other engineers to deliver the confidence needed in the design of the chip.

You will collaborate with the Functional Verification team to develop Design for Testing (DFT) environments, drive DFT strategy, and ensure our DFT solutions are properly verified for all usage scenarios.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving team behind Google’s groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full‑time position is $156,000–$229,000 plus bonus, equity and benefits. Our salary ranges are determined by role, level and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience and relevant education or training.

For more information about benefits at Google, visit the Google benefits portal.

Responsibilities

• Engage with DFT and Design teams at early design stage to define requirements for ATE tests and manufacturing test flow.
• Generate and verify ATE patterns, including debug level, production level, characterization, High Voltage Screen (HVS), High‑Temperature Operating Life (HTOL), Electrical Stress on Environment (ESOE) etc.
• Run pattern playbacks (VTPSIM) on all delivered patterns prior to silicon arrival to ensure high quality of pattern delivery.
• Own pattern translations and integrate DFT verification into the overall ASIC design flow.
• Prepare silicon debug verification strategy, test plan and readiness for testers, and participate in post‑manufacturing silicon bring‑up tasks.

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