Senior Analog & Mixed-Signal IC Designer

Anysilicon; New York (NY); Hybrid; USD 130,000 - 180,000; Full time

Job summary

Ferric, Inc. in New York City is seeking an Analog Mixed-Signal Circuit Design Engineer to develop advanced integrated voltage regulators for high-power SoCs and ultra-low power mobile platforms.

You will design analog/mixed-signal circuits, verify them through schematic and post-layout checks, and collaborate with cross-disciplinary teams to ensure robust IC implementations across CMOS nodes. This role emphasizes architectural input, device physics, and cutting-edge verification techniques.

Qualifications

• PhD or MSEE with 2+ years of full-custom CMOS design experience.
• Design experience in bandgaps, ADCs/DACs, PLLs, DLLs, LDOs, temperature sensors, switched-capacitor circuits, op-amps, comparators, and biasing circuits.

Responsibilities

• Design analog and mixed-signal circuits according to architectural requirements and specifications in various CMOS nodes.
• Contribute to architectural definition of designs and chip integration with business and application teams.
• Research and investigate new circuit techniques to enhance Ferric ICs.
• Perform analyses, design, and verification simulations to meet specs at schematic and post-layout levels.
• Document blocks, conduct design reviews, and participate in reviews.
• Collaborate with characterization, test, and applications engineers to verify and debug circuit blocks.

Skills

Cadence design tools

Low-power analog design

Mixed-signal circuit design

Architectural definition

Schematic & layout verification

Block design & analysis

Verilog, Python, MATLAB

Education

PhD or MSEE

Tools

Cadence Virtuoso

Spectre

Calibre DRC/LVS/PEX

CppSim

Job description

Ferric, Inc. in New York City is seeking an Analog Mixed-Signal Circuit Design Engineer to develop advanced integrated voltage regulators for high-power SoCs and ultra-low power mobile platforms.

You will design analog/mixed-signal circuits, verify them through schematic and post-layout checks, and collaborate with cross-disciplinary teams to ensure robust IC implementations across CMOS nodes. This role emphasizes architectural input, device physics, and cutting-edge verification techniques.