Senior AMS Verification Engineer: SystemVerilog/UVM Expert

Analog Devices, Inc.; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Analog Devices, Inc. is seeking a Senior AMS Design Verification Engineer to own verification planning and execution for complex mixed-signal ICs and subsystems.

You will translate specifications into scalable verification architectures, develop reusable SystemVerilog/UVM and real-number models, and drive coverage closure across digital, analog, and mixed-signal interfaces. This role collaborates with analog, digital, firmware and validation teams to deliver robust products from pre-silicon to

Qualifications

• SystemVerilog/UVM for block- to SoC-level verification.
• Real-number modeling and analog behavioral model development.
• Familiarity with SPI, I²C, AXI and other high-speed interfaces.
• Experience leading verification from planning to sign-off and regression cycles.

Responsibilities

• Own feature-based verification plans, requirements traceability, risk assessment, test strategy, and sign-off criteria for complex AMS IP, subsystems, and SoCs.
• Architect scalable, reusable verification environments that combine SystemVerilog/UVM, analog behavioral models, real-number models, and mixed-signal simulation.
• Develop and validate behavioral models in SystemVerilog real-number modeling, Verilog-AMS, or equivalent languages.
• Create constrained-random and directed tests, scoreboards, reference models, assertions, monitors, and functional coverage for analog-digital interactions, control loops, power modes, calibration, and fault conditions.
• Define measurable coverage goals; analyze gaps; drive closure; and communicate verification readiness and residual risk.
• Lead cross-domain debugging using waveforms, logs, assertions, schematics, and analog measurements.
• Build regression flows and automation to improve simulation throughput, reproducibility, and engineering productivity.
• Collaborate closely with analog, digital designers, firmware engineers, model developers, and post-silicon validation teams.

Skills

SystemVerilog/UVM

AMS Fundamentals

AMS Modeling

Mixed-Signal Simulation

Verification Planning

Verification Techniques

Power-Aware Verification

Scripting/Automation

Debug/Data Analysis

Interfaces/Context

Communication/Leadership

Education

Bachelor’s degree in EE/CE

Master’s degree preferred

Job description

Analog Devices, Inc. is seeking a Senior AMS Design Verification Engineer to own verification planning and execution for complex mixed-signal ICs and subsystems.

You will translate specifications into scalable verification architectures, develop reusable SystemVerilog/UVM and real-number models, and drive coverage closure across digital, analog, and mixed-signal interfaces. This role collaborates with analog, digital, firmware and validation teams to deliver robust products from pre-silicon to