Senior AMS Design Verification Engineer – Space Tech

Blue Origin; Cupertino (CA); On-site; USD 230,000 - 323,000; Full time

Benefits offered by this job

Medical, dental, vision

Life insurance

401(k) with company match

Paid parental leave

Short/long-term disability

Stock options

Paid time off

Education Support Program

Job summary

Blue Origin is seeking a Senior Staff or Principal AMS Design Verification Engineer to lead co-simulation and verification for complex SOCs. You will define the EDA environment, develop models, and drive innovative verification strategies in a collaborative, safety-focused culture.

You will create Verilog/SystemVerilog test benches, support analog/digital teams, and perform AMS simulations across multi-node processes. Relocation and up to 10% travel are included where needed.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• 7+ years of relevant industry experience.
• Hands-on CMOS analog mixed-signal design and verification.
• Verilog/SystemVerilog modeling of analog/mixed-signal circuits and systems.
• Proficient with Cadence Virtuoso for schematic creation and simulation.
• Proficient with Python and MATLAB.
• Strong communication skills.
• U.S. citizen or eligible to work in the U.S.

Responsibilities

• Define the co-simulation methodology and EDA infrastructure working with analog and digital teams.
• Create Verilog/SystemVerilog test benches and behavioral models of analog and mixed-mode circuits.
• Develop methodologies for block- and chip-level mixed-mode verification.
• Support analog and digital teams during model bring-up and usage.
• Perform AMS simulations.

Skills

AMS verification

Verilog/SystemVerilog

Cadence Virtuoso

Python

MATLAB

Scripting

Education

Bachelor’s degree in Electrical/Computer Engineering

MS/PhD in Electrical/Computer Engineering

Tools

Verilog/SystemVerilog

AMS simulation tools

Job description

Blue Origin is seeking a Senior Staff or Principal AMS Design Verification Engineer to lead co-simulation and verification for complex SOCs. You will define the EDA environment, develop models, and drive innovative verification strategies in a collaborative, safety-focused culture.

You will create Verilog/SystemVerilog test benches, support analog/digital teams, and perform AMS simulations across multi-node processes. Relocation and up to 10% travel are included where needed.