Senior AI-Driven RISC-V CPU Core Design Engineer

GlobalFoundries; Santa Clara (CA); On-site; USD 69,000 - 202,000; Full time

Job summary

GlobalFoundries is seeking recent graduates to become world-class CPU IP Design Engineers in Santa Clara, CA. You will own RTL development for an AI-enabled RISC-V CPU core, addressing functional features, performance, power, and area.

You’ll drive micro-architecture for critical blocks, design the vector core and its extensions, and collaborate with a multi-disciplinary team to optimize timing and physical design. A strong foundation in Verilog/SystemVerilog is required.

Qualifications

• Bachelor’s with 3-7 years or Master’s with 2-5 years of experience.
• Knowledge of SystemVerilog/Verilog/VHDL and CPU microarchitecture concepts.
• Experience with RTL design, verification, and timing/power considerations.

Responsibilities

• Drive micro-architecture and design of CPU core blocks.
• Design RISC-V Vector core and extensions.
• Develop AI-enabled matrix engine to augment vector CPU.
• Support verification and validate timing, area, and power.
• Collaborate with multi-functional team on SoC integration.

Skills

CPU architecture

SystemVerilog

Verilog/VHDL

RTL design

Python/Perl scripting

Education

Bachelor’s in CS/EE

Master’s degree (preferred)

Tools

Verilog simulators

Job description

GlobalFoundries is seeking recent graduates to become world-class CPU IP Design Engineers in Santa Clara, CA. You will own RTL development for an AI-enabled RISC-V CPU core, addressing functional features, performance, power, and area.

You’ll drive micro-architecture for critical blocks, design the vector core and its extensions, and collaborate with a multi-disciplinary team to optimize timing and physical design. A strong foundation in Verilog/SystemVerilog is required.