Senior AI Deployment Engineer for Chip Design

Cadence Design Systems

Oregon

Hybrid

USD 170,000 - 230,000

Full time

14 days+

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Job summary

Cadence Design Systems seeks a Principal AI Forward Deployment Engineer to embed with strategic semiconductor customers and operationalize Cadence's AI solutions across end-to-end silicon design flows.

You will translate frontend, physical-design, and methodology workflows into measurable productivity gains powered by flagship LLMs and Cadence AI tooling, serving as the trusted technical lead on-site with customers and driving ROI.

Qualifications

BS/MS/PhD in EE, ECE, CS or related discipline.
10+ years hands-on semiconductor/chip design across RTL, PD, CAD/methodology, or tape-out leadership.
Deep fluency with EDA flows and shipped silicon experience.
Proven ability to apply LLM/AI tools to deliver real engineering work (debug, RTL generation, copilots, RAG).
Excellent customer-facing communication with senior engineers and CAD leaders.
Bias to action, ownership, and shipping.
Willing to relocate to Portland, OR or be on-site as needed.

Responsibilities

Lead end-to-end deployment of Cadence AI/LLM solutions into customers' silicon design flows from RTL to packaging.
Architect and tune agentic workflows and pipelines on flagship LLMs to automate EDA tasks.
Map customer methodology onto Cadence AI building blocks and create reference flows.
Define and report KPIs: cycle-time reduction, engineer-hours saved, ROI.
Serve as trusted technical advisor during design reviews and roadmaps.
Guide IT/Sec on secure AI deployment and data governance.
Capture playbooks and mentor field teams.