Semiconductor Process Engineer

UST; Santa Clara (CA); On-site; USD 70,000 - 105,000; Full time

Benefits offered by this job

10 days of paid vacation

6 days of paid sick leave

401(k) retirement plan with matching

Medical, dental, vision insurance

Job summary

UST is seeking a Semiconductor Process Engineer – Associate III to join our team in Santa Clara, California. In this role, you will focus on wafer defect characterization and failure analysis within R&D or semiconductor manufacturing environments.

Your responsibilities include designing experiments, troubleshooting defect problems, and implementing new technologies. A Bachelor's or Master's in a relevant field and experience in semiconductor engineering are required. The position offers a compensation range of $70,000 – $105,000 per year and various employee benefits.

Qualifications

• 1-2 years of experience in semiconductor process engineering.
• Expertise in wafer defect analysis.
• Proficient in statistical analysis and experimental design.

Responsibilities

• Design, collect data, analyze and compile reports for defect reduction.
• Troubleshoot defect problems and perform Root Cause Analysis.
• Implement new technology to support defect study.

Skills

Semiconductor process engineering

Wafer defect analysis

Hands-on experience with SEM/FIB

Root Cause Analysis (RCA)

Statistical analysis

Education

Bachelor's or Master's in Electrical Engineering, Materials Science, Chemical Engineering, Physics, Microelectronics/Nanotechnology

Tools

DOE (Design of Experiments)

Metrology tools

Job description

Semiconductor Process Engineer – Associate III

Semiconductor Process / Defect Analysis Engineering role focused on wafer defect characterization and failure analysis in an R&D or semiconductor manufacturing environment.

Responsibilities

• Design, collect data, analyze and compile reports on process engineering experiments for defect reduction, within safety guidelines.
• Troubleshoot defect problems, perform Root Cause Analysis and resolve moderately difficult process engineering issues.
• Implement new technology, products and analytical instrumentation to support the defect study.
• Design the failure analysis (FA) DOE for key defect-critical components to troubleshoot wafer defect issues on key R&D programs and major customer escalations.
• Perform the FA, collect and analyze data within safety guidelines.
• Communicate FA observations and recommend the solution path in defect troubleshooting.
• Measure wafer defect/film properties, organize data/reports for review in supporting defectivity improvement by SEM/FIB.
• Prepare wafers for experimentation, including cleaning, loading wafers, prepare klarf files, evaluate and recommend performance of process system.

Qualifications

• Experience: 1-2 years.
• Semiconductor process engineering, wafer defect analysis expertise.
• Hands‑on experience with SEM/FIB operation, Failure Analysis (FA), Root Cause Analysis (RCA), defect metrology.
• Knowledge of semiconductor wafer fabrication, yield improvement & defect reduction, SEM/EDS/FIB principles, cleanroom & wafer handling, process engineering and metrology tools.
• Proficiency in DOE (Design of Experiments) and data analysis & reporting.
• Proficient with statistical analysis and experimental design.

Education

• Bachelor's or Master's in Electrical Engineering, Materials Science, Chemical Engineering, Physics, Microelectronics/Nanotechnology or related field.

Location

California

Compensation

$70,000 – $105,000 per year.

Benefits

Full‑time, regular employees accrue a minimum of 10 days of paid vacation per year, 6 days of paid sick leave, 10 paid holidays, and eligibility for paid bereavement leave and jury duty. Eligible for 401(k) retirement plan with matching. Medical, dental, vision insurance available for employee and dependents (US). Optional voluntary short‑term disability benefits, HSA, FSA. Part‑time employees receive 6 days paid sick leave and 401(k) matching. Temporary employees receive 6 days sick leave and 401(k) matching. All US employees receive benefits in accordance with local sick leave laws.

Equal Employment Opportunity

UST is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. We consider qualified applicants with arrest or conviction records in accordance with state and federal laws and "fair chance" ordinances. UST reserves the right to periodically redefine your roles and responsibilities.