Secure SoC/ASIC Verification Engineer

ZeroRISC; Boston (MA); On-site; USD 120,000 - 180,000; Full time

Job summary

zeroRISC seeks a SoC/ASIC Design Verification Engineer to develop, verify, and maintain silicon in security‑sensitive settings, including root‑of‑trust technology. You will build verification environments, write test plans and verification docs, diagnose regressions, and drive coverage closure while collaborating with architecture, design, software, and silicon validation teams.

Join a seed‑stage startup focused on open secure silicon, with opportunities to impact security solutions for critical

Qualifications

• 4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools
• Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments

Responsibilities

• Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off
• Build high quality verification environments at the chip/top and block levels following engineering best practices
• Write thorough verification documentation including test plans
• Diagnose, debug, and resolve regression failures and other errors
• Achieve coverage closure
• Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers

Skills

UVM

SystemVerilog

Formal verification

Testbenches

Verification environments

Education

Bachelor’s degree in Electrical Engineering or Computer Science

Equivalent experience

Tools

Python

Job description

zeroRISC seeks a SoC/ASIC Design Verification Engineer to develop, verify, and maintain silicon in security‑sensitive settings, including root‑of‑trust technology. You will build verification environments, write test plans and verification docs, diagnose regressions, and drive coverage closure while collaborating with architecture, design, software, and silicon validation teams.

Join a seed‑stage startup focused on open secure silicon, with opportunities to impact security solutions for critical