RTL Hardware Engineer

Darwin Recruitment; United States; Remote; USD 100,000 - 150,000; Full time

Job summary

A leading company is seeking an RTL Hardware Engineer to innovate on cryptographic accelerators using Fully Homomorphic Encryption (FHE). In this remote role, you will design, implement, and optimize RTL for next-gen silicon architectures, collaborating with a dedicated silicon team, enhancing your skills in a pioneering space.

Qualifications

• 5+ years of experience in RTL design with SystemVerilog or Verilog.
• Strong understanding of digital design principles and memory hierarchy.
• Experience in high-throughput architectures, ideally crypto or DSP.

Responsibilities

• Develop and implement RTL designs for cryptographic blocks.
• Collaborate with verification and synthesis teams for seamless integration.
• Optimize for performance, power, and timing closure.

Skills

RTL design

SystemVerilog

Verilog

digital design principles

Tools

Python

Perl

Tcl

Job description

RTL Hardware Engineer – Cryptographic Accelerators / FHE

Remote – USA | Contract – 6+ Months

About the Company:

Our client is building the foundational hardware layer for privacy-preserving computation, leveraging Fully Homomorphic Encryption (FHE) to enable secure processing of encrypted data. This is a unique chance to work on groundbreaking silicon that powers next-gen cryptographic workloads.

Role Overview:

We’re looking for an RTL Hardware Engineer to design, implement, and optimize custom hardware blocks for a novel FHE accelerator. You’ll work in a close-knit silicon team to bring new crypto architectures to life, from high-level concept to verified RTL.

Key Responsibilities:

• Develop and implement RTL designs for compute-intensive cryptographic blocks and data-paths.
• Work from architecture specifications to deliver optimized and scalable RTL.
• Collaborate closely with verification, synthesis, and physical design teams to ensure seamless integration and performance.
• Analyze and optimize for area, performance, power, and timing closure.
• Contribute to microarchitecture definition, design reviews, and documentation.

Ideal Background:

• 5+ years of experience in RTL design using SystemVerilog, Verilog, or similar.
• Strong understanding of digital design principles, pipelining, memory hierarchy, and finite state machines.
• Experience working with high-throughput, low-latency architectures, ideally in crypto, DSP, or accelerator design.
• Familiarity with synthesis and timing analysis flows.
• Comfortable working from architecture down to gate-level handoff.

Nice to Have:

• Exposure to cryptographic algorithms or FHE concepts.
• Experience collaborating with verification and physical design teams across the silicon lifecycle.
• Familiarity with scripting (Python, Perl, or Tcl) to support automation and design workflows.
• Startup or R&D hardware experience.

Contract Details:

• Duration: 6+ months, with strong potential for extension
• Location: Remote – USA
• Engagement: W2, 1099, or Corp-to-Corp

Darwin Recruitment is acting as an Employment Business in relation to this vacancy.

Reece Waldon