RTL Design Engineer, TPU

Careers; United States; On-site; USD 163,000 - 236,000; Full time

Job summary

Google Sunnyvale, CA is seeking an RTL Design Engineer for TPU architecture. You will design SystemVerilog RTL, define microarchitecture, and collaborate with software and system hardware teams to deliver scalable AI/ML accelerator IP.

The role emphasizes verification, timing closure, and integration within SoCs, with opportunities to influence TPU design and drive cutting-edge hardware innovations.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• Experience with scripting languages.
• Master's degree or PhD with emphasis on computer architecture (preferred).
• 8 years of experience in ASIC design (preferred).
• Experience interacting with software, system hardware, and cross-functional teams.
• Experience with chip management, clocking, reset, and peripherals (I2C, SPI, UART, etc.).
• Understanding of digital design fundamentals including synchronous/asynchronous logic, state machines and bus protocols.

Responsibilities

• Create and review management and control subsystem design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products per guidelines.
• Collaborate with architecture and power teams to evaluate features and impact.
• Work with DV teams to create test plans to verify and debug RTL.
• Coordinate with physical design teams to ensure timing closure.

Skills

RTL design

SystemVerilog

Digital design fundamentals

Cross-functional collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree or PhD in EE/CE/CS (preferred)

Job description

RTL Design Engineer, TPU

Location: Sunnyvale, CA, USA

Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with scripting languages.

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 8 years of experience in ASIC design.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will join a team working on SoC-level Register-Transfer Level (RTL) design for our data center accelerators. You will design RTL Intellectual Property (IP) with the focus on management and control subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., clocking, reset, error handling, debug, chip management and SOC chassis etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts. You will utilize a background in RTL design, and the ability to lead multi-faceted efforts involving many stakeholders.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware, our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

Compensation

• US: $163,000 - $236,000 (USD) + 15% bonus target + equity + benefits

Responsibilities

• Work separately to create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

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See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

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Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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