RTL Design Engineer, Machine Learning Accelerators

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Bonus target 15%

Equity

Job summary

Google Sunnyvale, CA, USA is seeking a Mid RTL Design Engineer for Machine Learning Accelerators. You will help shape AI/ML hardware acceleration, work on TPU architecture, and collaborate with software and system teams to integrate complex digital designs.

Requires a Bachelor's degree in EE/CE/CS or related field and 4 years in custom silicon design (SoCs/ASICs). Proficiency in Verilog or SystemVerilog and scripting (Python or Perl) is expected. Master’s or PhD in a relevant field is preferred.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, computer science, or related field, or equivalent practical experience.
• 4 years of experience with custom silicon design (SoCs, ASICs).
• Experience with RTL design using Verilog or SystemVerilog.
• Experience interacting with software, architecture, and cross‑functional teams.
• Experience with a scripting language (e.g., Python or Perl).
• Experience applying engineering best practices (code review, testing, refactoring).
• Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms.
• Knowledge of high performance and low power design techniques.

Responsibilities

• Understand the overall application of the chip, proposing and developing improvements in overall design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Work with software teams on functionality, interfaces, and documentation.

Job description

RTL Design Engineer, Machine Learning Accelerators

Google Sunnyvale, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

• Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience.
• 4 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.).
• Experience with RTL design using Verilog or SystemVerilog.

Preferred qualifications:

• Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture.

Experience interacting with software, architecture, and other cross‑functional teams.

• Experience with a scripting language (e.g., Python or Perl).
• Experience applying engineering best practices (e.g., code review, testing, refactoring).
• Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms.
• Knowledge of high performance and low power design techniques.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

Learn more about benefits at Google .

• Understand the overall application of the chip, proposing and developing improvements in overall design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Work with software teams on functionality, interfaces, and documentation.

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Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.