Senior RTL Design Engineer for AI Processor SoC

Mythic Ai.Com; Austin (TX); On-site; USD 120,000 - 225,000; Full time

Job summary

Mythic is seeking experienced RTL Design Engineers to design and implement RTL for next-generation AI processors. You will work on a novel digital dataflow architecture, including scheduling subsystems, interconnect fabrics, and DMA engines, driving high performance and efficiency.

The team collaborates with architecture, custom analog IP, compiler, verification, emulation, and post-silicon groups to ensure seamless integration. 8+ years in RTL design and strong Verilog skills are highly valued.

Qualifications

• 8+ years of RTL design, microarchitecture, and architecture development.
• Solid understanding of computer architecture fundamentals (pipelines, caches, memory hierarchies).
• Hands-on experience with scheduling fabrics, high-performance interconnects, DMA engines, memory controllers, or datapath/control logic.
• Proficiency in Verilog/SystemVerilog and RTL coding guidelines.
• Familiarity with timing constraints, physical design considerations, and EDA flows.
• Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.

Responsibilities

• Design and implement RTL for Mythic's next-generation AI processor.
• Contribute to a novel digital dataflow architecture, including scheduling subsystem, interconnect fabric, and DMA engines.
• Develop and optimize high-performance, low-power datapaths, controllers, memory subsystems, and interconnects.
• Collaborate with architects and verification engineers to define microarchitecture and ensure correctness.
• Drive timing closure by working with synthesis and physical design teams.
• Participate in design reviews and improve RTL coding practices and methodologies.

Skills

NoC architectures

Python scripting

problem solving

communication

Education

Bachelor’s, Master’s, or Ph.D. in Electrical/Computer Engineering or CS

Tools

Verilog/SystemVerilog

EDA flows

simulation

synthesis

linting

static timing analysis

Job description

Mythic is seeking experienced RTL Design Engineers to design and implement RTL for next-generation AI processors. You will work on a novel digital dataflow architecture, including scheduling subsystems, interconnect fabrics, and DMA engines, driving high performance and efficiency.

The team collaborates with architecture, custom analog IP, compiler, verification, emulation, and post-silicon groups to ensure seamless integration. 8+ years in RTL design and strong Verilog skills are highly valued.