RTL Design Engineer

Anysilicon; Palo Alto, Northern (CA, KY); Hybrid; USD 140,000 - 230,000; Full time

Job summary

Normal Computing Corporation in Palo Alto, CA is seeking an experienced engineer to design and verify digital logic for cutting-edge thermodynamic hardware and AI-oriented ASICs, with a hybrid work model. You will implement SystemVerilog RTL, build verification environments, and collaborate across architecture and physical design to meet tight timing and tapeout goals.

The role emphasizes production RTL experience, a proven tapeout track record, and strong debugging in both simulation and formal

Qualifications

• Hands-on production RTL in SystemVerilog.
• Experience authoring verification environments using UVM, cocotb, or formal tools.
• At least one tapeout experience from any company size.
• Ability to operate across design and verification disciplines.
• Experience with datapaths, pipelines, or custom logic with unspecified microarchitecture upfront.
• Strong debugging skills in simulation and formal verification.

Responsibilities

• Design and verify digital logic for thermodynamic hardware.
• Write synthesizable RTL in SystemVerilog for various blocks.
• Author functional verification environments using UVM, cocotb, or formal tools.
• Collaborate with architecture to translate specifications into microarchitectures.
• Work with physical design on timing closure and floorplanning constraints.
• Develop and maintain simulation infrastructure and regression pipelines.
• Participate in design reviews and contribute to architectural decisions.
• Support tapeout preparation and post-silicon bring-up.

Skills

SystemVerilog

RTL design

ASIC/SoC verification

Debugging

UVM verification

Tools

UVM

Cocotb

Formal verification tools

Job description

Normal Computing Corporation, Palo Alto, CAHybrid work

Job Description:

Normal Computing is a pioneering company that develops silicon technology to harness thermal noise for computational purposes, achieving significant efficiency in AI inference. With a collaborative team across multiple global locations, Normal Computing is backed by substantial investment and is focused on innovative ASIC design and AI-native EDA systems.

Responsibilities:

• Design and verify digital logic for thermodynamic hardware.


• Write synthesizable RTL in SystemVerilog for various blocks.


• Author functional verification environments using UVM, cocotb, or formal tools.


• Collaborate with architecture to translate specifications into microarchitectures.


• Work with physical design on timing closure and floorplanning constraints.


• Develop and maintain simulation infrastructure and regression pipelines.


• Participate in design reviews and contribute to architectural decisions.


• Support tapeout preparation and post-silicon bring-up.

Qualifications:

• Hands-on experience with production RTL in SystemVerilog.


• Experience in authoring verification environments in UVM, cocotb, or formal tools.


• At least one tapeout experience from any company size.


• Ability to operate across design and verification disciplines.


• Experience with datapaths, pipelines, or custom logic with unspecified microarchitecture upfront.


• Strong debugging skills in simulation and formal verification.

Skills:

• Proficiency in SystemVerilog and RTL design.


• Knowledge of UVM and verification methodologies.


• Experience in ASIC or SoC design.


• Ability to collaborate with architects and physical designers.


• Familiarity with AI chip design and verification processes.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services


• Verification


• Packaging & Wafer


• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services


• Verification


• Packaging & Wafer


• Semiconductor IP

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