RTL ASIC Design Engineer — DRAM Controllers

micron; Minneapolis (MN); On-site; USD 86,000 - 146,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Benefits package

Job summary

Micron Technology is seeking an ASIC Digital Design Engineer to design RTL for next-gen DRAM memory controllers using SystemVerilog and to collaborate across analog, verification, physical design, and validation teams. You will develop HDL models, run simulations, and support chip bring-up while leveraging AI-enabled tools to enhance productivity and design quality.

The role requires 0-2 years in digital/ASIC RTL development, a degree in Electrical/Computer Engineering, and strong communication

Qualifications

• 0-2 years of experience in digital design or ASIC RTL development.
• Bachelor's or Master's in Electrical/Computer Engineering.
• Skilled in SystemVerilog RTL design.
• Knowledge of verification methods, high-speed interfaces, and ASIC principles.
• Programming or scripting using Python or Linux shells.
• Basic understanding of analog/mixed-signal concepts (PLLs, DLLs, CDRs).
• Strong communication and cross-team collaboration.

Responsibilities

• Design RTL for DRAM memory controllers in SystemVerilog.
• Collaborate with cross-functional teams across analog, verification, and physical design.
• Develop and validate HDL models; support simulation and co-simulation.
• Assist in chip bring-up, debugging, and validation.
• Apply AI-enabled tools to improve design workflows and productivity.

Skills

SystemVerilog

Digital design

Python

Scripting

Communication

AI tools familiarity

Collaboration

Education

Electrical/Computer Engineering degree

Tools

Synthesis tools

Linting tools

Equivalency checking tools

Formal verification tools

Simulation tools

Job description

Micron Technology is seeking an ASIC Digital Design Engineer to design RTL for next-gen DRAM memory controllers using SystemVerilog and to collaborate across analog, verification, physical design, and validation teams. You will develop HDL models, run simulations, and support chip bring-up while leveraging AI-enabled tools to enhance productivity and design quality.

The role requires 0-2 years in digital/ASIC RTL development, a degree in Electrical/Computer Engineering, and strong communication