Remote Senior Design Verification Engineer (SV/UVM)

Tenstorrent; United States; Remote; USD 140,000 - 200,000; Full time

Job summary

Tenstorrent seeks a Sr. Design Verification Engineer to lead verification for state‑of‑the‑art digital designs, owning verification strategy and building advanced environments using SystemVerilog and UVM.

You will mentor engineers and collaborate with architecture, design, and software teams to ensure robust, high‑quality compute engines powering AI and HPC workloads. The role is remote with a Munich, Germany base and offers learning across silicon bring-up, post‑silicon validation, and

Qualifications

• Lead the definition and execution of verification plans for complex digital blocks and systems.
• Drive verification methodologies and strategy across projects, setting best practices.
• Build advanced test environments using SystemVerilog and UVM and execute testbenches and coverage.
• Collaborate with architecture, design and software teams to align on specs and debug issues.
• Mentor junior engineers to foster a high performing verification team.

Responsibilities

• Define verification strategy and drive execution across multiple projects.
• Develop and maintain advanced test environments and test benches.
• Collaborate with hardware and software teams to ensure correct integration.

Skills

Verification leadership

SystemVerilog

UVM

Testbench development

Formal verification

Cross-functional

SoC architecture

Education

Tools

Questa

VCS

Job description

Tenstorrent seeks a Sr. Design Verification Engineer to lead verification for state‑of‑the‑art digital designs, owning verification strategy and building advanced environments using SystemVerilog and UVM.

You will mentor engineers and collaborate with architecture, design, and software teams to ensure robust, high‑quality compute engines powering AI and HPC workloads. The role is remote with a Munich, Germany base and offers learning across silicon bring-up, post‑silicon validation, and