Remote Principal Engineer, Physical Design for SoC - Equity

Baya Systems; Oregon; Híbrido; USD 180 000 - 240 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Salary commensurate with experience

Performance incentives

Comprehensive medical, dental, and vis

401(k) retirement plan

Equity

Resumo da oferta

Baya Systems is seeking a Principal Engineer-Physical Design for a fully remote role across the United States. The candidate will own RTL-to-GDS flows, floor planning, and PDV across high-performance SoC designs, collaborating with micro-architects to optimize performance, power and area.

The position requires a bachelor’s degree in EE/CE and 5 years in related roles, with expertise in floor planning, clock trees, PD flow automation, ICC, and SoC architecture.

Qualificações

• Bachelor’s degree in Electrical Engineering or Computer Engineering or related field.
• 5+ years of experience in physical design or related roles.
• Experience with RTL-to-GDS flow and PD tooling.
• Strong knowledge of floor planning, clock trees, PDV and DRC/LVS.

Responsabilidades

• Own RTL to GDS physical implementation flows including synthesis, floor-planning, place and route, clock tree synthesis, timing and power closure, PDV and final PD sign-off.
• Own physical design and implementation of high-performance designs from block to system level.
• Collaborate with Micro-architects to balance performance, power and area.
• Perform PDV flows and design rule checks to ensure physical design quality.
• Provide design recommendations and best practices for PPA improvements.

Conhecimentos

RTL to GDS flow

Floor planning

PD validation

Clock tree synthesis

PDV flows

SoC Architecture

Formação académica

Bachelor's degree in Electrical Engineering or Computer Engineering or related degree

Ferramentas

ICC

Descrição da oferta de emprego

Baya Systems is seeking a Principal Engineer-Physical Design for a fully remote role across the United States. The candidate will own RTL-to-GDS flows, floor planning, and PDV across high-performance SoC designs, collaborating with micro-architects to optimize performance, power and area.

The position requires a bachelor’s degree in EE/CE and 5 years in related roles, with expertise in floor planning, clock trees, PD flow automation, ICC, and SoC architecture.