Remote FPGA/Systems Software Engineer — Low-Latency

Objective Partners; Chicago (IL); On-site; USD 150,000 - 230,000; Full time

Job summary

Objective Partners invites a seasoned systems software engineer to join a remote team building ultra-low-latency execution software. You will own drivers to diagnostic frameworks and optimize microsecond-level performance for high-frequency workflows.

You will collaborate with hardware designers and software peers, focusing on C++14/17, Linux kernel development, PCIe DMA, and network stacks to push latency boundaries in a fast-paced, ownership-driven environment.

Qualifications

• 5+ years in systems programming and performance tuning.
• Proficient in C++14/17 and Python.
• Deep Linux kernel and driver experience.
• Experience with PCIe, DMA, and hardware interfaces.
• Strong TCP/IP, Ethernet, and networking knowledge.
• Familiarity with SystemVerilog/Verilog.
• Experience with Wireshark and hardware debugging.
• Exposure to FPGA vendor toolchains.
• Excellent communication and collaboration.

Responsibilities

• Architect and maintain high-speed C++ interfaces that integrate hardware components with core execution platforms.
• Develop Linux device drivers and DMA/PCIe latency optimizations.
• Collaborate with hardware engineers during lab bring-up and testing.
• Build diagnostic tools and automation suites in C++ and Python.
• Analyze system performance using logs, traces, and telemetry.
• Tune low-latency network stacks and custom protocols.

Skills

C++14/17

Linux kernel

PCIe DMA

Python scripting

SystemVerilog/Verilog

Education

B.S. CS/EE or related

Tools

Wireshark

Xilinx toolchain

Intel FPGA toolchain

Job description

Objective Partners invites a seasoned systems software engineer to join a remote team building ultra-low-latency execution software. You will own drivers to diagnostic frameworks and optimize microsecond-level performance for high-frequency workflows.

You will collaborate with hardware designers and software peers, focusing on C++14/17, Linux kernel development, PCIe DMA, and network stacks to push latency boundaries in a fast-paced, ownership-driven environment.