Remote-Eligible Digital IC Design Engineer (DSP/High-Speed)

AttoTude inc.; United States; Remote; USD 120,000 - 180,000; Full time

Job summary

AttoTude inc. is seeking an experienced Digital IC Design Engineer to join our team, working on cutting-edge DSP and mixed-signal ICs. This hands-on role demands deep technical expertise and collaboration with a team of senior engineers to achieve ambitious tape-out goals.

The role involves writing RTL SystemVerilog, developing testbenches, and driving timing closure across multiple process technologies. Occasional travel to the Bay Area is expected for a remote position.

Qualifications

• 5+ years of hands-on CMOS digital IC design experience.
• Strong SystemVerilog coding/verification experience.
• Proficiency in Tcl, Python, and shell scripting.
• Experience with PCIe, AXI, UCIe, SPI, I2C, APB interfaces.
• Excellent communication and teamwork skills.

Responsibilities

• Flow system level requirements into architecture and design specifications.
• Collaborate with Comm Systems Engineers to optimize power, performance, and area.
• Document and write RTL SystemVerilog to meet system requirements.
• Write SystemVerilog testbenches and test cases to verify designs.
• Develop timing constraints, synthesize, and perform STA and timing closure.
• Perform gate-level simulations and support lab/HW-SW integration post-tapeout.
• Coordinate with cross-functional teams to meet tape-out timelines.
• Stay updated with trends in wideband high-speed IC design and apply improvements.
• Occasional travel to the Bay Area (<10%) for a remote position.

Skills

SystemVerilog

Tcl

Python

Shell scripting

Communication

Teamwork

Education

Bachelor's Degree in Electrical Engineering

Master's Degree in Electrical/Computer Engineering

Tools

XCelium

Genus

Tempus

Conformal

Voltus

Matlab

Job description

AttoTude inc. is seeking an experienced Digital IC Design Engineer to join our team, working on cutting-edge DSP and mixed-signal ICs. This hands-on role demands deep technical expertise and collaboration with a team of senior engineers to achieve ambitious tape-out goals.

The role involves writing RTL SystemVerilog, developing testbenches, and driving timing closure across multiple process technologies. Occasional travel to the Bay Area is expected for a remote position.