Radar SoC Verification Manager

Texas Instruments; United States; Remote; USD 130,000 - 180,000; Full time

Job summary

Texas Instruments is seeking a Verification Engineer for its RADAR product line to own IP/SS/SOC DV from specification through post-silicon verification. You will lead and mentor cross-functional teams, shaping verification strategy, plans and infrastructure across multiple SoC programs.

Responsibilities include DV environment ownership, TB development, signoff based on coverage, and collaboration with architecture, RTL, PD, DFT, systems, and FW teams to ensure high-quality silicon delivery in

Qualifications

• 8+ years of DV experience in IP/SS/SOC/post-silicon DV with a relevant degree.
• Experience leading DV projects and teams across IP/SS/SOC.
• Strong background in functional/firmware verification and post-silicon carryover.
• Hands-on with Verilog/SystemVerilog, UVM, and DV flows.
• Familiarity with safety standards and cross-functional collaboration.

Responsibilities

• Own DV across IP, subsystem and SoC from spec to post-silicon verification.
• Build, mentor and scale verification teams for multiple SoC programs.
• Lead verification strategy, methodology, infrastructure and plans.
• Define verification plans to ensure regression traceability and signoff.
• Verify IP/SS/SOC in RTL/PARTL, GLS/PAGLS and DV environments.
• Collaborate with Architecture, RTL, PD, DFT, FW and apps teams.
• Achieve SoC DV signoff based on regressions and coverage metrics.

Skills

DV leadership

C-based DV

UVM/SystemVerilog

Cadence tools

AXI/AHB/APB

ARM/DSP multi-processor

ISO26262 awareness

Communication skills

Problem solving

Verilog/VHDL debugging

Education

Bachelor or Master in EE/ECE/CS or related

Tools

Cadence Xcelium

Cadence vManager

Formal DV tools

Safety verification tools

Job description

Texas Instruments is seeking a Verification Engineer for its RADAR product line to own IP/SS/SOC DV from specification through post-silicon verification. You will lead and mentor cross-functional teams, shaping verification strategy, plans and infrastructure across multiple SoC programs.

Responsibilities include DV environment ownership, TB development, signoff based on coverage, and collaboration with architecture, RTL, PD, DFT, systems, and FW teams to ensure high-quality silicon delivery in