Quantum Internship: Classical Systems for QEC

Riverlane; Boston (MA); Hybrid; USD 48,000 - 58,000; Full time

Job summary

Riverlane’s engineering internship in Boston offers hands-on work on quantum error correction, interfacing quantum and classical systems. You’ll investigate classical architectures to support fault-tolerant quantum computers and work with researchers across QEC theory, decoding, software and hardware.

You will model and simulate architectures, explore decoding workloads, and contribute to reproducible research code and documentation.

Qualifications

• You must be a current student at the time of application, studying towards a Bachelor’s degree (second year or later), Master’s degree.
• Experience in quantum error correction or fault-tolerant quantum computing, computer architecture or quantum-classical systems, decoding algorithms or error-correcting codes, FPGA/ASIC or digital hardware design, and experience developing research software.

Responsibilities

• Contribute to a research project focused on classical systems and architectures for scalable quantum error correction.
• Investigate methods to reduce compute, communication, memory, latency or power for QEC.
• Develop algorithms, simulations or architectural models to evaluate approaches.
• Explore trade-offs between decoding performance and classical resource requirements.
• Consider QEC workloads across software, FPGA, ASIC or other architectures.
• Collaborate with researchers across QEC theory, decoding, software and hardware.
• Analyze results and present findings via talks and reports.
• Produce reproducible research code and documentation.

Skills

Python

C

C++

Programming proficiency

Education

Bachelor’s or Master’s student (2nd year or later)

Tools

RTL

SystemVerilog

FPGA

ASIC

Job description

Riverlane’s engineering internship in Boston offers hands-on work on quantum error correction, interfacing quantum and classical systems. You’ll investigate classical architectures to support fault-tolerant quantum computers and work with researchers across QEC theory, decoding, software and hardware.

You will model and simulate architectures, explore decoding workloads, and contribute to reproducible research code and documentation.