Quantum Computing Research Intern: QEC & Co-Design

Riverlane; Boston (MA); On-site; USD 63,000 - 90,000; Full time

Job summary

Riverlane is seeking an engineering intern to explore classical computing architectures for scalable quantum error correction. The role sits at the intersection of quantum error correction, computer architecture, and hardware-software co-design.

You will work with Riverlane researchers in Cambridge, MA, supervised by a dedicated mentor, contributing to understanding how QEC systems meet performance needs of large quantum computers.

Qualifications

• Pursuing a PhD in a technical field (CS/CE/EE/Physics/Math).
• Experience with computer architecture or quantum-classical systems.
• Experience with decoding algorithms or error-correcting codes.
• Hardware design: FPGA/ASIC or digital hardware.
• Proficiency in Python, C, C++ or similar.
• Strong problem-solving and analytical skills.
• Ability to communicate complex ideas clearly.
• Legal authorization to work in the United States for the internship duration.

Responsibilities

• Contribute to a research project on classical systems for scalable QEC.
• Investigate methods to reduce compute, communication, memory, latency or power.
• Develop algorithms, simulations or architectural models to evaluate approaches.
• Explore trade-offs between decoding performance and resources.
• Consider QEC workloads across software, FPGA, ASIC or other architectures.
• Collaborate with researchers across QEC theory, decoding and hardware.
• Analyze results and present findings in discussions and reports.
• Produce reproducible research code and documentation.

Skills

Python

C

C++

Research software

Analytical thinking

Communication

Education

PhD in CS/CE/EE/Physics/Math

Tools

FPGA

SystemVerilog

RTL

ASIC/workflows

Job description

Riverlane is seeking an engineering intern to explore classical computing architectures for scalable quantum error correction. The role sits at the intersection of quantum error correction, computer architecture, and hardware-software co-design.

You will work with Riverlane researchers in Cambridge, MA, supervised by a dedicated mentor, contributing to understanding how QEC systems meet performance needs of large quantum computers.