Principal UVM Digital Verification Engineer

ED Wallach Search Group; Cambridge (MA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading company in digital design is seeking a Principal UVM Digital Verification Engineer to tackle complex verification challenges in FPGAs and ASICs. The role involves applying modern verification strategies and mentoring less experienced engineers while collaborating with multidisciplinary teams. Candidates should have a strong background in engineering and relevant experience in systems analysis and verification.

Qualifications

• 7-10 years in systems analysis or related fields.
• Experience with verification and test plans.
• Ability to develop UVM Agents and VIPs for industry standard buses.

Responsibilities

• Develop solutions to complex verification challenges.
• Mentor team members and provide constructive feedback.
• Lead verification teams and define methodologies.

Skills

Mathematical skills

Engineering theories and procedures

Collaboration

Verbal communication

Written communication

Organizational skills

Time management

Adaptability

Quick learning

Education

Bachelor’s degree in Aerospace, Electrical, Mechanical Engineering

Master’s degree preferred

Tools

MBSE tools (SysML, MATLAB/Simulink)

SystemVerilog

Industry simulators (Questasim, Xcelium, VCS)

Scripting languages (Python, Perl, Bash)

Linux environment

Job description

Location: Cambridge, MA

Security Clearance: US Citizen/Clearable

Our Digital Design Team is seeking a motivated and experienced Principal UVM Digital Verification Engineer to tackle verification challenges in FPGAs and ASICs.

In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in embedded security, cryptography, signal and image processing, navigation, and communications.

Job Description:

Duties/Responsibilities:

1. Independently develop solutions to complex problems, including requirements gathering, proposing solutions when customer requirements are unclear, and adapting to changes.
2. Serve as a Subject Matter Expert (SME) in Systems Engineering.
3. Provide insights and suggest design modifications based on analysis outcomes, applying analysis techniques across disciplines.
4. Identify program/system-level risks and develop mitigation strategies.
5. Develop, document, and teach best practices to less experienced engineers.
6. Mentor team members, recognizing their strengths and weaknesses, and providing constructive feedback.
7. Collaborate with stakeholders and external partners in a multidisciplinary environment.
8. Translate requirements into technical and architectural decisions.
9. Develop and integrate modeling and analysis techniques, including multi-domain qualitative models.
10. Present results supporting system-level analysis and real-time decision-making.
11. Communicate technical concepts effectively with customers, engineers, managers, and stakeholders.

Skills/Abilities:

• Excellent mathematical skills.
• Strong understanding of engineering theories and procedures.
• Ability to collaborate within diverse, multidisciplinary teams.
• Excellent verbal and written communication skills.
• Strong organizational skills and attention to detail.
• Effective time management skills to meet deadlines.
• Knowledge of multiple problem domains and ability to adapt to evolving priorities.
• Quick learner in new domains.

Education:

Bachelor’s degree in Aerospace, Electrical, Mechanical, or relevant Engineering field; Master’s preferred.

Experience:

• 7-10 years in systems analysis or related fields.
• Experience with MBSE tools like SysML, MATLAB/Simulink, and integrating descriptive modeling tools with simulation tools.

Additional Job Responsibilities:

• Develop verification approaches, author and execute verification plans, utilize formal analysis tools.
• Lead verification teams, define test-bench architecture, and verification methodologies.
• Lead multidisciplinary teams, contribute to various projects, and develop next-generation digital hardware platforms.

Technical Skills:

• Fluent in SystemVerilog, including SVA.
• Experience with industry simulators (Questasim, Xcelium, VCS).
• Familiarity with IEEE bus standards, DDR3/DDR4, Amba Axi protocols.
• Knowledge of constrained-random testing, coverage-driven verification, and formal analysis.
• Proficiency in scripting languages (Python, Perl, Bash).
• Ability to work in a Linux environment.

Additional Requirements:

• Strong analysis and problem-solving skills.
• Experience developing verification and test plans.
• Ability to develop UVM Agents and VIPs for industry standard buses.
• Experience working with RTL designers to resolve simulation issues.
• Implement cover groups, work on coverage closures, and perform code reviews.
• Mentor junior engineers.

Applicants must obtain and maintain a government security clearance.

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