Principal Design Verification Engineer

The Fountain Group; United States; Remote; USD 100,000 - 125,000; Full time

Job summary

An innovative firm is seeking a Principal Design Verification Engineer to lead the verification of high-performance data transfer protocols in semiconductor designs. This role is pivotal in ensuring the integrity and performance of networking solutions used in high-speed computing and AI accelerators. With a focus on cutting-edge technologies, you will verify protocols like Ethernet and PCIe, configure high-speed SERDES, and validate ARM processor subsystems. Join a dynamic team dedicated to pushing the boundaries of semiconductor technology in a fast-paced environment where your expertise will make a significant impact.

Qualifications

• 15+ years in ASIC/SoC Design Verification required.
• Expertise in high-speed data transfer protocols and SERDES is essential.

Responsibilities

• Verify high-speed protocols for compliance and performance.
• Develop SystemVerilog/UVM testbenches and conduct coverage-driven verification.

Skills

ASIC/SoC Design Verification

High-speed data transfer protocols

SystemVerilog/UVM

Python

Perl

Error injection testing

Tools

VCS

Questa

Xcelium

Job description

This position can be Remote within the continental US.

We are looking for a Principal Design Verification Engineer to lead the verification of high-performance, packet-based data transfer protocols in cutting-edge semiconductor designs. This role focuses on ensuring the integrity, reliability, and performance of networking and interconnect solutions used in high-speed computing, AI accelerators, and data centers.

Key Responsibilities:

• Verify high-speed protocols (Ethernet, Infiniband, PCIe) for compliance and performance.
• Configure & validate high-speed SERDES and die-to-die interconnects for chiplet-based architectures.
• Verify ARM processor subsystems, ensuring integration and cache coherence.
• Validate JTAG/SBUS functionality and implement error injection tests.
• Develop SystemVerilog/UVM testbenches and conduct coverage-driven verification.

Qualifications:

• 15+ years in ASIC/SoC Design Verification.
• Expertise in high-speed data transfer protocols, SERDES, and chiplet interconnects.
• Hands-on experience with ARM subsystems, JTAG/SBUS, and error injection.
• Proficiency in SystemVerilog/UVM, Python, or Perl.
• Experience with industry-standard simulation tools (VCS, Questa, Xcelium).

Preferred:

• Formal verification, FPGA prototyping, and AI/HPC chip experience.

Join us to work on next-generation semiconductor designs in a fast-paced, innovative environment!

Seniority level

Mid-Senior level

Employment type

Contract

Job function

Industries: Computer Hardware Manufacturing and IT Services and IT Consulting