Principal SoC DFT Engineer

Nokia Corp.; San Jose (CA); Hybrid; USD 160,000 - 297,000; Full time

Job summary

Nokia Corp. is seeking a Principal DFT Engineer to drive ASIC DFT implementations for the Network Infrastructure Optical Network group.

You will own DFT insertion end-to-end from RTL to post-silicon, collaborating with architecture, IP design, Physical Design and product engineers to achieve first-pass silicon success. Hands-on DFT implementation and verification across BIST, MBIST, BISR, Boundary Scan and JTAG are required, with strong TCL scripting and test coverage focus.

Qualifications

• Bachelor's degree in computer science, Electrical Engineering or related fields with 8+ years of experience OR Master’s/PhD with 5+ years.

Responsibilities

• Lead DFT insertion from RTL/netlist through post-silicon debug.
• Perform DFT implementation and verification across BIST, MBIST, BISR, boundary scan and JTAG.
• Develop and validate DFT timing constraints for scan, BIST, and test modes.
• Create TCL scripts to automate DFT insertion, verification and analysis flows.
• Collaborate with RTL, IP design, Physical Design and product engineers to resolve DFT issues and drive first-pass silicon success.

Skills

DFT implementation

Logic BIST

MBIST

BISR

Boundary Scan

JTAG

ATPG

TCL scripting

Timing constraints

Debugging

Education

Bachelor's degree in CS/EE

Master's/PhD in CS/EE

Tools

EDA tools

IP/BBIST tools

Job description

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group

Your responsibilities

You will be working on DFT architecture and implementation across logic BIST, MBIST, BISR, Boundary Scan, and JTAG. This is a highly execution-driven role requiring end-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design and product engineers to achieve first pass silicon success.

Perform hands-on DFT implementation and verification, including:

• Logic BIST and scan compression
• MBIST and BISR
• Boundary Scan (IEEE 1149.x) insertion
• JTAG insertion and connectivity
• High-speed analog/mixed signal IP integration
• Execute DFT verification, debug, and DFT DRC closure
• Identify, debug, and resolve DFT rule violations at both block and top levels
• Run, analyze, and debug DFT/RTL checks, working with design teams to close violations
• Generate, simulate, and debug MBIST and logic ATPG patterns
• Analyze test results and drive test coverage improvement and closure
• Develop and validate DFT timing constraints for scan, BIST, and test modes
• Create and maintain TCL scripts to automate DFT insertion, verification, and analysis flows
• Support hierarchical DFT implementation and resolve integration issues
• Collaborate with RTL and Physical Design teams to address DFT-related design issues
• Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up and debug
• Assist with ATE pattern conversion and debug as needed

Experience with gate-level simulations and debugging with industry simulator tools

Your skills and experience

You Have:

• Bachelor’s degree in computer science, Electrical Engineering or related fields and 8 years
  of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5 years of experience.
• 5+ years of hands-on DFT implementation experience
• Strong proficiency with EDA tools , including:
  • Logic BIST insertion and verification
  • MBIST / BISR insertion and verification
  • Boundary Scan (IEEE 1149.x)
  • JTAG and HS Analog/mixed signal IP IOBIST integration
  • ATPG pattern generation and coverage analysis
• Proven ability to resolve DFT DRCs, connectivity issues, and testability problems
• Strong TCL scripting skills for DFT automation and flow execution
• Experience developing and validating scan and test-mode timing constraints
• End-to-end DFT lifecycle experience, from RTL/netlist through silicon debug
• Strong debugging skills, attention to detail, and sense of ownership
• Excellent verbal and written communication skills

At Nokia, we want every candidate to be able to perform their best. If you need any adjustments or support during the recruitment process, please let us know. All requests are treated confidentially.

Job Info

• Job Category Applied R&D
• Posting Date 05/05/2026
• Job Schedule Full time
• Job Type Experienced
• Job Identification 32544
• Will NSA/CAPS approval be required? (E.g., accessing a US Customer Network?) No
• Laptop - support with ordering needed Yes
• Salary Range US Salary range: $159,782.61- $296,739.13
• Regular or Temporary Regular

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