Senior RTL Design Engineer

Precision Labs; Texas; Hybrid; USD 120,000 - 200,000; Full time

Benefits offered by this job

Medical insurance

Dental & Vision

HSA employer contribution

Gym/Well-being benefits

Headspace subscription

Job summary

SambaNova Systems is seeking an RTL Design Engineer to contribute to the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration platforms. You will own blocks within a subsystem, write and debug RTL, and guide them through implementation, tape-out and silicon bring-up with senior engineers.

Ideal candidates have a strong foundation in digital logic, SystemVerilog, and computer architecture, plus experience trading off power, performance and area.

Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 5+ years of experience in ASIC RTL design.
• Strong SystemVerilog RTL design skills for high‑speed ASICs.
• Experience trading off power, performance and area.
• Knowledge of AXI, PCIe, Ethernet, and HBM or DDR interconnects.
• Experience with RTL linting, CDC and LEC.

Responsibilities

• Own blocks within a larger RTL subsystem for the RDU ASICs.
• Write and debug RTL and carry blocks through implementation.
• Guide designs through tape‑out and silicon bring‑up.
• Collaborate with principal engineers, design verification and physical design.

Skills

SystemVerilog RTL design

Digital logic design

Computer architecture

Python scripting

Linux shell

Git

Clock domain crossing

Education

Bachelor's in Electrical/Computer Engineering or CS

M.S. or Ph.D. in EE/CE/CS

Tools

Digital logic synthesis tools

Static timing analysis tools

Linting/CDC/LEC tools

Job description

SambaNova is a leader in next‑generation AI infrastructure, delivering a full‑stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi‑turn agents, code generation, and long‑running applications. RDUs are packaged into SambaRack, rack‑scale hardware that lets customers deploy state‑of‑the‑art models with better performance, greater energy efficiency, and faster time to value.

About the team

The RTL design team builds the compute datapath, on‑chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape‑out: RTL implementation, PPA trade‑offs, quality gates like lint, CDC, and LEC, and timing closure with

About the role

SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape‑out, and silicon bring‑up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture

Required Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science
• 5+ years of experience in ASIC RTL design
• Solid foundation in computer architecture and digital logic design
• Strong SystemVerilog RTL design skills for high‑speed, high‑performance ASICs
• Experience making design decisions that trade off power, performance, and area
• Knowledge of industry‑standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
• Experience with digital logic synthesis tools and static timing analysis
• Proficiency with industry‑standard tools for linting, clock domain crossing, and logical equivalence checking
• Experience implementing SystemVerilog Assertions to check design intent
• Familiarity with tools and simulators for hardware performance analysis and tuning
• Familiarity with Git for managing release cycles
• Scripting skills in Python and Linux shell

Preferred Qualifications

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
• Exposure to a full ASIC development cycle through tape‑out and production silicon
• Interest in or knowledge of AI workload acceleration techniques
• Experience with low‑power design techniques such as clock gating and DVFS at advanced process nodes
• Exposure to emulation or FPGA prototyping platforms for pre‑silicon validation

Base Salary Range: $120,000 — $200,000 USD

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well‑being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.