Formal Verification Engineer

Tenstorrent; Santa Clara (CA); On-site; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Formal Verification Engineer to verify high‑performance RISC‑V CPUs and AI compute platforms using formal methods. You will develop properties, run proofs, and analyze failures in collaboration with CPU architects and RTL designers.

The role is remote, based out of North America or Spain, and open to candidates at various experience levels with offers aligned to level reached in the interview process.

Qualifications

• 6+ years of experience in design verification or formal verification for CPUs, SoCs or complex digital designs.
• Strong SystemVerilog skills including writing and debugging SVA.
• Hands-on experience with formal verification methodologies and tools.

Responsibilities

• Develop and apply formal verification methods to verify complex CPU architectures and microarchitectures.
• Analyze counterexamples and RTL behavior to identify root causes of failures.
• Collaborate with CPU architects and RTL designers to improve design quality and verification coverage.

Skills

Formal verification

SystemVerilog

Python

RTL debugging

Counterexample analysis

Tools

SVA

Formal verification tools

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a Formal Verification Engineer to help ensure the correctness of our next generation of high-performance RISC-V CPUs and AI compute platforms. You’ll use formal methods to prove complex hardware behavior, uncover corner cases that simulation may miss, and give architects and RTL designers confidence in the correctness of their designs.You’ll work closely with CPU architects, RTL designers, and other DV engineers to develop properties, build formal verification environments, analyze failures, and drive issues to closure. This is a hands‑on opportunity to apply formal techniques to challenging problems in modern processor design.

This role isremote, based out of North America or Spain.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A verification engineer who enjoys solving complex problems and finding bugs that are difficult to expose through traditional simulation.
• Comfortable thinking about hardware behavior in terms of properties, invariants, assumptions, assertions, and proofs.
• A strong debugger who can analyze counterexamples, understand RTL behavior, and determine the root cause of failures.
• Collaborative and curious, with an interest in working closely with architects and RTL designers to improve design quality.
• Excited by the challenges of verifying high-performance CPUs and complex digital hardware.

What We Need

• 6+ years of experience in design verification, formal verification, or related RTL verification for CPUs, SoCs, ASICs, or complex digital designs.
• Hands‑on experience with formal verification methodologies and tools, including property checking, assertions, assumptions, constraints, and coverage analysis.
• Strong SystemVerilog skills, including experience writing and debugging SVA.
• Solid understanding of digital design and computer architecture; experience with CPU pipelines, caches, interfaces, control logic, or other complex microarchitecture is highly valuable.
• Strong programming and scripting skills in Python, Tcl, C/C++, or similar, with excellent debugging and problem‑solving abilities.

What You Will Learn

• Gain deep experience applying formal verification to high‑performance, out‑of‑order RISC‑V CPU designs.
• Learn how to identify which hardware behaviors are best verified through formal methods versus simulation, emulation, and other DV techniques.
• Develop expertise in writing scalable properties and proofs for complex control logic and interacting microarchitectural blocks.
• Learn how architectural intent translates into formal properties, assumptions, and measurable verification goals.
• Work alongside world‑class CPU architects and RTL engineers on next‑generation processors for AI, HPC, and high‑performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

As set forth in Tenstorrent’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A \"disabled veteran\" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service‑connected disability.

A \"recently separated veteran\" means any veteran during the three‑year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An \"active duty wartime or campaign badge veteran\" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An \"Armed forces service medal veteran\" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.