Principal Physical Design Engineer

ZipRecruiter; San Jose (CA); On-site; USD 140,000 - 225,000; Full time

Job summary

An innovative company is seeking a Principal Physical Design Engineer to lead the development of cutting-edge cellular infrastructure solutions. This role involves providing technical leadership in ASIC design, driving integration efforts, and ensuring the successful mass production of state-of-the-art radio technologies. With a focus on energy efficiency and operational excellence, this position offers the opportunity to work with a talented team at the forefront of radio technology. If you're passionate about making a significant impact in a dynamic environment, this is the perfect opportunity for you.

Benefits

Pre-IPO stock options

Comprehensive group health plan

Matching 401(k)

Training reimbursement

Paid vacation

Paid sick leave

Paid holidays

Maternity/paternity leave

Jury leave

Qualifications

• 20+ years of experience in ASIC physical design.
• Expert in full-chip formal verification and physical verification.
• Hands-on experience in block-level floor-planning and timing closure.

Responsibilities

• Drive chip level integration of digital and analog IPs.
• Contribute to ASIC integration efforts including floor planning and clock distribution.
• Manage quality deliverables and execute excellent physical designs.

Skills

ASIC physical design

Chip assembly process

Physical Design

Integration

Physical Verification

Scripting for automation

Interpersonal skills

Education

MS in Electrical Engineering

Tools

Cadence digital EDA toolset

Innovus

Quantus

Tempus

Conformal

Job description

Job Description

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation.

To learn more about GreenWave Radios and hear what our employees have to say, visit the GreenWave certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website.

As a Principal Physical Design Engineer, you will be responsible for providing technical leadership in developing novel/game-changing cellular infrastructure radio and ASIC solutions. You will be a key contributor to our solutions features, architectures, device functional specifications, and performance. Your primary responsibilities include providing technical guidance on block physical implementation to a multi-site team of engineers, determining project requirements, driving the chip integration of large SOCs, efficiently delegating and tracking tasks, and supporting other discipline teams to bring the SoC device to successful mass production.

This full-time California position is located in San Jose.

Key Responsibilities:

• Drive chip level integration of digital and analog IPs and provide technical direction
• Contribute to all aspects of ASIC integration effort including floor planning, clock and power distribution, global signal planning, I/O planning, and hard IP integration
• Perform block-level implementation using place and route techniques to meet area/timing and power requirements when needed.
• Drive clock tree planning and implementation to achieve the best energy, performance, and area goals
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
• Work directly with the Synthesis/Timing Team to ensure design closure
• Manage quality deliverables and execute excellent physical designs in a timely manner

Job Qualifications:

• MS in Electrical Engineering plus 20 or more years of experience in ASIC physical design
• Significant experience in chip assembly process of large SOCs in advanced process nodes
• Able to contribute as an individual contributor on block level physical implementation, P&R
• Deep understanding of Physical Design, Integration, STA, and Physical Verification
• Expert in full-chip Formal verification, signal EM, IR-drop analysis, STA, and physical verification.
• Hands-on experience in block-level floor-planning, power planning, placement, clock tree synthesis, routing, LVS/DRC/ERC, timing closure, signoff, and engineering change orders (ECO's)
• Knowledge and skills in optimizing PPA through floor-planning, placement and timing constraints, useful skew, and similar techniques
• Experience with the Cadence digital EDA toolset (Innovus / Quantus / Tempus / Conformal)
• Ability to use scripting to automate process flow
• Team player with good interpersonal and communication skills

Desirable Skills:

• Experience with DFT flow
• Ability to be proactive and have a strategic mindset in addition to having tactical problem-solving experience
• Familiarity with industry-standard interfaces

Compensation and Benefits:

At InnoPhase, our compensation package includes base pay and pre-IPO stock options. The base pay range for this role is between $140K-$225K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.