Principal FPGA/ASIC Design Lead — Open RAN

GreenWave Radios™; Irvine (CA); On-site; USD 190,000 - 225,000; Full time

Job summary

InnoPhase Inc., DBA GreenWave Radios, seeks a seasoned Principal Engineer/Manager to lead a high-impact team building next-generation cellular infrastructure Front Haul Gateway solutions in FPGA and ASIC. You’ll own architecture through production and work with experts across design, verification, firmware, and system engineering.

The role requires 20+ years in FPGA/SoC, MS/PhD in EE, deep Verilog/SystemVerilog, AMBA/USB/PCIe experience, and Linux-based wireless software collaboration.

Qualifications

• MS or PhD in Electrical Engineering or equivalent.
• 20+ years of FPGA/SoC development and leadership experience.
• Expertise in Verilog/SystemVerilog and front-end tooling (simulation, linting, CDC, formal verification).

Responsibilities

• Lead and mentor a small team of FPGA/ASIC design engineers.
• Own solution architecture end-to-end—from requirements to production.
• Drive SoC architecture, CPU/bus/memory subsystems, IP integration, and physical implementation.
• Collaborate with system engineering on Radio product specifications.
• Coordinate with IP, verification, firmware, software, and production teams to meet milestones.
• Refine development methodologies and enforce design quality standards.
• Collaborate with embedded Linux-based wireless software team.

Skills

FPGA/SoC leadership

Verilog / SystemVerilog

Scripting: Python, Tcl, Perl, C/C++

SystemVerilog verification

Cross-functional collaboration

Education

MS or PhD in Electrical Engineering or equivalent

Tools

Xilinx Vivado

EDA tools (DFT/DFM, ATPG)

Job description

InnoPhase Inc., DBA GreenWave Radios, seeks a seasoned Principal Engineer/Manager to lead a high-impact team building next-generation cellular infrastructure Front Haul Gateway solutions in FPGA and ASIC. You’ll own architecture through production and work with experts across design, verification, firmware, and system engineering.

The role requires 20+ years in FPGA/SoC, MS/PhD in EE, deep Verilog/SystemVerilog, AMBA/USB/PCIe experience, and Linux-based wireless software collaboration.