Senior FPGA/SoC Architect & Open RAN Lead

GreenWave Radios™; Irvine (CA); On-site; USD 190,000 - 225,000; Full time

Benefits offered by this job

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Job summary

GreenWave Radios seeks a Digital Design Principal Engineer/Manager in Irvine, CA to lead a small team delivering next‑gen cellular infrastructure radio Front Haul Gateway (FHGW) solutions in FPGA/ASIC. You’ll own architecture, specifications, and production flow for high‑performance programmable logic with embedded Linux software.

You’ll guide design, verification, firmware, and system engineering across cross‑functional teams, shaping a market‑leading product with a strong emphasis on energy

Qualifications

• 20+ years in FPGA and SoC development with leadership experience.
• MS or PhD in Electrical Engineering or equivalent.
• Deep Verilog/SystemVerilog expertise and front-end tooling.
• Hands-on with packet processing designs (e.g., Ethernet, ORAN/eCPRI).
• Experience with AMBA AXI/AHB/APB and FPGA implementation flow.
• DFT/DFM, SCAN ATPG, BIST, and fault coverage experience.
• SystemVerilog verification methodologies and scripting skills.
• C/C++, Perl, Tcl, Python programming and strong communication.

Responsibilities

• Lead and mentor a small FPGA/ASIC design team, including planning and scheduling.
• Own end-to-end solution architecture from marketing requirements to production‑quality design.
• Define micro‑architecture, CPU/bus/memory subsystems, IP integration, physical implementation.
• Collaborate with system engineering on Radio product specs and alignment.
• Coordinate with IP, verification, firmware, software, and production teams to resolve issues.
• Improve development methods and enforce design quality, including CDC checks and formal verification.
• Work with embedded Linux‑based software teams that complement the FPGA/ASIC stack.

Skills

FPGA/SoC leadership

Technical mentoring

Verilog/SystemVerilog

AMBA AXI/AXI4

Synthesis & timing analysis

DFT/DFM & ATPG

SystemVerilog verification

Scripting: C/C++, Python, Perl, Tcl

Communications & collaboration

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Xilinx Vivado

Job description

GreenWave Radios seeks a Digital Design Principal Engineer/Manager in Irvine, CA to lead a small team delivering next‑gen cellular infrastructure radio Front Haul Gateway (FHGW) solutions in FPGA/ASIC. You’ll own architecture, specifications, and production flow for high‑performance programmable logic with embedded Linux software.

You’ll guide design, verification, firmware, and system engineering across cross‑functional teams, shaping a market‑leading product with a strong emphasis on energy