Principal FEOL/MOL integration Engineer

Tokyo Electron Limited; Albany (OR); On-site; USD 148,000 - 209,000; Full time

Job summary

TEL in Albany, TX seeks a Principal FEOL/MOL integration Engineer to own end-to-end route architecture, drive e-test capability, and lead cross-business-unit projects. The role focuses on building groundbreaking test flows and ensuring data-driven decisions across TEL’s tooling portfolio.

You will collaborate with TEL BUs, factories, and partners to verify processes for advanced logic devices, maintaining quality standards and rigorous documentation throughout the workflow.

Qualifications

• Master’s degree or PhD with semiconductor experience.
• 8+ years of related semiconductor engineering experience.
• FEOL/MOL process integration experience from flow definition through wafer execution.

Responsibilities

• Serve as the principal technical authority for FEOL/MOL integration and drive direction.
• Define and build new process integration routes across litho, etch, films, wets, and CMP for test vehicles.
• Establish and own e-test capability including parametric test structures and probe card coordination.
• Lead cross-BU projects coordinating roadmaps, tools, and deliverables.
• Design, execute, and demonstrate integration solutions on TEL internal vehicles with data-driven analysis.
• Own lot management including DOEs, metrology setup, and data evaluation.
• Support stakeholders in resolving integration and process issues with TEL equipment capabilities.
• Maintain rigorous quality control and data integrity standards.

Skills

FEOL/MOL integration

Electrical test / parametric test

Cross-BU project leadership

DOE design

Data analysis

Statistical software (JMP)

Strong communication

Self-management

Windows/MS Office

Metrology tools

Education

Master’s degree in Electrical Engineering

PhD in related field

Bachelor’s degree in Engineering

Tools

SIVIEW MM/SM

CDSEM

Cross-sectional SEM

Quartz PCI

Job description

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Job Description

Principal FEOL/MOL integration Engineer

Location: Albany, TX

Job Description

As a **Principal Process Integration Engineer** within our FEOL/Middle-of-Line process integration organization, you will operate as a senior individual contributor and technical authority for the team. This is a fab-facing role: you will define and stand up new process integration routes, build out electrical test (e-test) capability from the ground up, and serve as the principal technical owner for cross-business-unit (X-BU) programs that bring TEL’s tool and process portfolio together on internal test vehicles.

You will work closely with TEL’s onsite business units (BUs), factories, and ecosystem partners to verify and integrate processes that demonstrate the benefits of TEL technologies for advanced logic and memory devices. Success in this role means owning route architecture end to end - from flow definition through wafer execution, electrical characterization, and data-driven decision-making - and setting the technical standard for the engineers around you.

Responsibilities

• Serve as the **principal technical authority** for FEOL/MOL integration, driving direction, priorities, and technical quality through hands‑on execution and mentorship as a senior individual contributor (no direct reports).

• **Define and build new process integration routes** across litho, etch, films, wets, and CMP for FEOL/MOL test vehicles, including flow definition, mask/reticle planning, and split strategy.

• **Establish and own e-test (electrical test) capability** for the team: parametric test structure and PCM design, test chip planning, probe card / test program coordination, wafer-level parametric extraction, and correlation of electrical results back to unit process and integration knobs.

• **Lead cross-business-unit (X-BU) projects**, coordinating roadmaps, tool capabilities, and deliverables across TEL BUs, factories, and onsite partners to meet current and future customer needs through standard and novel integration flows.

• Design, execute, and demonstrate proposed integration solutions on TEL internal vehicles, including statistical analysis of results.

• Own lot management including process splits, DOEs, metrology setup, and data analysis/evaluation.

• Support internal and external stakeholders in resolving integration and process issues through current and future TEL equipment capability.

• Maintain rigorous quality-control, documentation, and data-integrity practices, and set those standards for the team.

Required & Preferred Skills

• Demonstrated **FEOL/MOL process integration** experience with a strong track record of building new processing routes from flow definition through wafer execution. *(Required)*

• Hands‑on **electrical test / parametric test** experience — test structure design and interpretation (e.g., MOSCAP, TLM, Kelvin, Van der Pauw, BEOL daisy chains), PCM/wafer-level parametrics, and probe/test‑program coordination. *(Strongly preferred / required for the e‑test build‑out)*

• Experience **leading cross‑functional or cross‑BU technical projects**, including planning and scheduling. *(Required)*

• Lot management skills using SIVIEW MM/SM. *(Preferred)*

• Metrology and analysis tool operation, including inline CDSEM and cross‑sectional SEM. *(Required)*

• Knowledge of experiment design (DOE) and techniques for tool and process optimization. *(Required)*

• EUV lithography and/or 193i immersion experience. *(Preferred)*

• Strong data‑analysis skills; experience with JMP or equivalent statistical software, Excel, and measurement/analysis software (e.g., Quartz PCI). *(Preferred)*

• Excellent verbal and written communication, including technical presentations. *(Required)*

• Strong self‑management, teamwork, collaboration, and problem‑solving skills. *(Required)*

• Proficiency with personal computer, peripherals, and standard software (MS Windows, MS Office, networking). *(Required)*

Typical Education and Experience

• Master’s degree in a related science/engineering field — preferably Electrical Engineering, Materials Science/Engineering, Chemical Engineering, Mechanical Engineering, Chemistry, or Physics — with a minimum of 8 years of related semiconductor-industry engineering experience; **or** PhD with a minimum of 5 years’ experience; **or** Bachelor’s degree with a minimum of 10 years’ experience.

• Semiconductor integration experience is required; unit‑process experience across litho (scanner/track recipe setup and mask installation), etch, films, wets, and/or CMP is beneficial.

• Prior experience as a principal/senior individual contributor or driving multi‑stakeholder technical programs is preferred.

• U.S. work authorization is required.

Physical Demands and Work Conditions

This role operates in both an office and a cleanroom/fab setting. Regular hands‑on fab work is expected. Candidates must be able to work in a cleanroom environment, including wearing specialized cleanroom attire (gowns, gloves, masks, hairnets) for extended periods and lifting/carrying FOUPs. The role routinely uses standard office equipment and typically involves 4-6 hours per day at a computer, with the remaining time in the cleanroom or lab. The position may require occasionally lifting office products and supplies up to 35 pounds. Candidates should be comfortable working in a highly regulated, meticulous setting where adherence to strict cleanliness and safety protocols is essential.

Diversity creates an innovative culture. TEL US is an Equal Employment Opportunity / Affi‑ mative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, national origin, protected veteran status, disability status, sexual orientation, gender identity or expression, marital status, genetic information, or any other characteristic protected by law. Equal Opportunity Employer/Minorities/Females/Disabled/Veterans.

Individual pay is determined based on multiple factors, including but not limited to location, experience, skills, job‑related knowledge, relevant education, certifications, and/or training. In addition to base salary, we offer (full‑time regular employees) a comprehensive benefits package and, for certain roles, eligibility in our bonus plan and long‑term incentives as applicable. The talent advisor can share more details about total compensation for the role in your location during the hiring process.

About TEL

Since its founding in 1963, TEL has grown into a global organization that engineers, manufactures, sells, and services wafer‑processing and semiconductor production equipment (SPE), as well as flat‑panel display (FPD) and thin‑film photovoltaic (PVE) equipment. As the world market‑share leader across several product lines, TEL plays a key role in the evolving global semiconductor industry.

Salary Ranges

$148,319.86 - $209,424.67

Individual pay is determined based on multiple factors, including but not limited to location, experience, skills, job‑related knowledge, relevant education, certifications, and/or training. In addition to base salary, we offer (full time regular employees ) a comprehensive benefits package and for certain roles eligibility in our bonus plan and long‑term incentives as applicable. The talent advisor can share more details about total compensation for the role in your location during the hiring process.

Diversity creates an innovative culture. TEL US is an Equal Employment Opportunity / Affi‑ mative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, national origin, protected veteran status, disability status, sexual orientation, gender identity or expression, marital status, genetic information, or any other characteristic protected by law.

Subsidiary

TOKYO ELECTRON AMERICA, INC.