Principal Engineer Electrical

0909 SP - Orbital Space Systems; United States; On-site; USD 98,400 - 147,600; Full time

Benefits offered by this job

Health insurance

Life and disability insurance

Paid time off (PTO)

Job summary

0909 SP - Orbital Space Systems is seeking an FPGA/ASIC Engineer – Level 3 for their location in Gilbert, AZ. This role involves designing and verifying FPGA and ASIC products for space applications, requiring strong RTL design experience and a background in aerospace.

The salary range offers between $98,400 to $147,600, alongside several benefits including health insurance and paid time off. The position may involve some travel and is contingent on program awards.

Qualifications

• 5 years experience or 3 years with a Master’s degree or 1 year with a PhD.
• Industry experience in FPGA design, simulation, and V&V.
• Expertise achieving timing closure on FPGA designs.

Responsibilities

• Conduct research and requirements analysis for C&DH products.
• Perform design, coding, test bench creation, and verification.
• Manage FPGA/ASIC synthesis, timing analysis, and place & route.

Skills

HDL design for FPGA and/or ASIC applications

FPGA/ASIC verification via simulation and emulation

FPGA design for space environments or applications

Experience in RTL design for aerospace environment

Proficient in FPGA design flow

Education

Bachelor’s degree in a STEM discipline

Tools

EDA tools (Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim)

Job description

Position Summary

Northrop Grumman's Space Systems Sector is looking for an FPGA/ASIC Engineer – Level 3 in Gilbert, AZ.

Relocation & Travel

Relocation assistance: None. Travel: Yes, 10% of the time.

Job Description

Responsibilities include, but are not limited to, research, requirements analysis, systems architecture, design, coding, test bench design, verification, synthesis, and place & route for Command and Data Handling (C&DH) products. The engineer will specialize in FPGA/ASIC for space applications.

Core Responsibilities

• HDL design for FPGA and/or ASIC applications.
• FPGA/ASIC verification via simulation and emulation (lab testing).
• FPGA/ASIC synthesis, timing analysis, and place & route.
• FPGA design for space environments or space applications.

Basic Qualifications

• Bachelor’s degree in a STEM discipline from an accredited university and 5 years of experience, or 3 years with a Master’s degree, or 1 year with a PhD.
• Experience in RTL design for an aerospace environment or space application.
• Proficient in FPGA design flow including RTL/gate level simulation, synthesis, place & route, static timing analysis, and power analysis.
• Industry experience in FPGA design, simulation, and V&V.

Preferred Qualifications

• Advanced degree in Electrical or Computer Engineering.
• Top Secret clearance.
• Experience with EDA tools (Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify).
• Implementation of digital signal or image processing algorithms on FPGAs.
• Expertise achieving timing closure on FPGA designs and generating test benches for complete functional simulation.
• Experience with test benches using System Verilog and UVM.
• Hardware‑level debugging experience with signal generators, logic analyzers, digital oscilloscopes, and embedded FPGA debugging tools.

Compensation and Benefits

Primary level salary range: $98,400.00 – $147,600.00. Eligibility for overtime, shift differential, discretionary bonus, and long‑term incentives for senior roles. Benefits include health insurance, life and disability insurance, savings plan, company‑paid holidays, and paid time off (PTO) for vacation and personal business.

Additional Information

Please be aware that this position is contingent upon capturing program award(s) and obtaining and maintaining associated business and/or customer funding.

Equal Opportunity Employer

Northrop Grumman is an Equal Opportunity Employer. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO.