Principal Physical Design

Micron; Boise (ID); On-site; USD 160,000 - 260,000; Full time

Benefits offered by this job

Benefits overview

Paid time off

Paid holidays

Job summary

Micron Technology is seeking a Principal Physical Design Engineer to provide technical leadership for advanced DRAM digital design implementation and signoff methodologies. You will drive physical design from RTL through tapeout, focusing on timing closure, power integrity, EMIR analysis, and design reliability across memory products.

You will collaborate across architecture, RTL, implementation, CAD, and technology teams, develop scalable physical design solutions to meet PPA targets, mentor

Qualifications

• Master's or Bachelor's with extensive ASIC physical design experience and strong STA, SI/PI, and design signoff.
• Experience with floorplanning, place & route, clock tree synthesis, and timing closure.
• Experience with industry tools and scripting for automation.

Responsibilities

• Lead physical design implementation of complex DRAM digital designs and tapeout.
• Drive power integrity strategies and signoff methodologies including EMIR and IR drop.
• Collaborate with architecture, RTL, CAD, and technology teams to resolve timing/congestion issues.
• Develop methodology improvements, automation, and provide technical leadership.
• Mentor engineers and influence future memory product roadmaps.

Skills

Python scripting

Tcl scripting

Automation

Education

Master's degree in Electrical Engineering or equivalent

Bachelor's degree with 10+ years of ASIC physical design experience

Tools

ICC2

Fusion Compiler

PrimeTime

PrimePower

RedHawk

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Summary

Micron is seeking a Principal Physical Design Engineer to provide technical leadership for advanced DRAM digital design implementation and signoff methodologies. This role will drive physical design execution from RTL through tapeout, with a strong focus on timing closure, power integrity, EMIR analysis, and design reliability. The engineer will collaborate across architecture, RTL, implementation, CAD, and technology teams to develop scalable physical design solutions that achieve power, performance, area (PPA), and reliability targets for next‑generation memory products. Additionally, this individual will lead methodology innovation, mentor engineers, and influence the future roadmap for physical design and power integrity across the organization.

Responsibilities

• Lead physical design implementation of complex DRAM digital designs, including floorplanning, place and route, clock tree synthesis, timing closure, and tapeout activities.
• Drive power integrity strategies and signoff methodologies, including PDN planning, IR drop analysis, electromigration (EM) verification, and EMIR signoff.
• Collaborate with multi-functional teams to resolve timing, congestion, power, signal integrity, and reliability challenges at both block and full-chip levels.
• Develop and deploy methodology improvements, automation solutions, and guidelines to improve build quality, efficiency, and scalability.
• Mentor engineers and provide technical leadership while influencing future memory products through innovation in physical design and signoff methodologies.

Minimum Qualifications

Master's degree in Electrical Engineering (or equivalent) with 8+ years of experience, or Bachelor's degree with 10+ years of experience in ASIC physical design. Strong expertise in physical design implementation flows including floorplanning, place and route, clock tree synthesis, timing closure, and design signoff. Hands‑on experience with STA, signal integrity, power integrity, physical verification, and advanced process technologies. Proficiency with industry‑standard physical design and signoff tools such as Synopsys IC Compiler II (ICC2), Fusion Compiler, PrimeTime, PrimePower, and RedHawk (or equivalent). Strong scripting and automation skills using Python, Tcl, or similar languages Demonstrated ability to drive multi-functional technical initiatives and influence engineering organizations.

Preferred Qualifications

Experience developing physical design, power delivery network (PDN), or EMIR methodologies for large-scale ASIC, SoC, or memory products. Expertise in power integrity signoff, including static and dynamic IR drop analysis, electromigration verification, current profiling, and IDD modeling. Experience driving methodology transformation, tool deployment, and engineering process improvements across organizations. Demonstrated technical leadership, mentoring, and ownership of projects across multiple product generations. Strong communication, problem-solving, and collaboration skills, with experience bringing to bear AI‑assisted technologies and Generative AI tools to improve engineering efficiency and innovation.

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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To learn more about Micron, please visit micron.com/careers

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at [e-mail] or 1-800-336-8918 (select option #3)

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

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