Sr. Staff Engineer, Photonics Design

Alumni Ventures; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Ayar Labs, located in San Jose, CA, seeks a Sr. Staff Engineer in Photonics Design to lead the photonic device layer. This role involves defining component requirements, engaging with partners in the Taiwan semiconductor ecosystem, and architecting design tools critical for product development.

The ideal candidate has over six years of experience in integrated photonic device design, along with a strong foundation in photonic device physics and simulation tools. The position offers a competitive salary between $180,000 and $240,000.

Qualifications

• 6+ years of commercial experience in silicon photonics.
• Deep understanding of photonic device physics.
• Strong experience in simulation and design tools.

Responsibilities

• Own the device roadmap and set performance targets.
• Engage directly with the Taiwan semiconductor ecosystem.
• Architect design and analysis tools for the team.

Skills

Silicon photonics

Design of photonic devices

Python programming

Process integration

Optoelectronic components

Education

B.S. in Electrical or Optical Engineering

M.S. or PhD in integrated photonics

Tools

FDTD simulation tools

Design tools for optical devices

Job description

Location: San Jose, CA

Job Id:631

# of Openings:0

Sr. Staff Engineer, Photonics Design

Location: San Jose (on-site)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we use light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next‑generation AI scale‑up architectures.

We're looking for a Sr. Staff Engineer to own the photonic device layer of that solution. You will define what our components need to achieve, determine what's physically achievable from leading‑edge processes, and drive the device roadmap from simulation through high‑volume manufacturing. This is a role for someone who thrives on hard, under‑specified problems — where the right answer isn't in the literature and the process isn't quite doing what you need it to do.

You’ll engage directly with partners across the Taiwan semiconductor ecosystem — not just designing to the PDK you’re given, but influencing what that process can achieve. And you'll shape the design and analysis infrastructure your team depends on: the simulation automation, layout flows, and verification frameworks are yours to architect, not inherit.

What You’ll Own

• Device roadmap. Own the device roadmap for integrated photonic components: set performance targets, assess process feasibility, and drive development from simulation through production.
• Foundry partnership. Engage directly with the Taiwan semiconductor ecosystem to push process capability in service of product requirements — not just consuming the PDK, but influencing what it does.
• Design infrastructure. Architect and extend the team's design and analysis tools: simulation automation, layout flows, verification frameworks, and custom code the broader team depends on.
• Debug and yield. Lead device-level debug, failure analysis, and yield investigation across development and production runs.
• Cross‑functional co‑design. Drive component performance in close collaboration with system, laser, packaging, firmware, and circuit design teams — the device layer connects all of them.

Required Qualifications

• B.S. or equivalent experience in Electrical Engineering, Optical Engineering, or related field
• 6+ years of commercial experience in silicon photonics or integrated photonic device design
• Deep understanding of photonic device physics: electro‑optic modulators, photodetectors, gratings, couplers, micro‑ring resonators
• Proficiency with simulation and design tools for passive and active optical devices (e.g., FDTD, charge transport simulation)
• Strong Python skills; demonstrated experience writing well‑structured code and extending a shared codebase as part of a team
• Track record of taking opto‑electronic components from design through manufacturing: design, debug, and validation
• Track record of solving problems that don't have obvious solutions — in device physics, process integration, or system‑level tradeoffs

Preferred Qualifications

• M.S. or PhD with integrated photonics focus
• Experience engaging directly with foundry process teams on process development or customization beyond standard PDK offerings
• High‑speed design and RF test experience: VNA, BERT, wafer‑level screening
• Statistical analysis of process and test data; DOE methods
• Familiarity with co‑packaged optics: system requirements, CPO architectures, and the industry transition from pluggable to on‑board optics
• Experience with electro‑optic reliability modeling and testing
• Demonstrated use of AI tools to achieve meaningful productivity gains in design or analysis workflows — e.g., device optimization, AI‑assisted code development

Salary Range: $180,000 - $240,000

Note to Recruiters

Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.

Ayar Labs is an affirmative action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.