Principal DVT Engineer — Post-Silicon Validation Lead

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. in Irvine, CA is seeking an experienced Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs powering AI and hyperscale optical networking.

You will drive silicon characterization and readiness for production. As a technical leader, you will shape validation strategy, build infrastructure, and collaborate across Architecture, RTL, Firmware, Systems, and Customer Engineering.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 8+ years of hands-on post-silicon validation, DVT, or silicon bring-up experience with complex ASICs or SoCs.
• Proven experience bringing first silicon to production in networking, data center, AI, or HPC products.
• Strong understanding of silicon debug methodologies and root-cause analysis.
• Extensive experience with lab equipment and high-speed validation tools.
• Proficiency in Python for automation, regression, and data analysis.
• Ability to interpret schematics, board design, and power sequencing.

Responsibilities

• Lead post-silicon validation and characterization from first silicon through production.
• Develop validation plans covering functionality, performance, interoperability, stress testing, and reliability.
• Enable first silicon bring-up using JTAG, scan, and embedded debug features.
• Validate high-speed interfaces such as PCIe, Ethernet, SerDes, and CXL.
• Utilize lab equipment including oscilloscopes, BERTs, protocol analyzers, network analyzers, and logic analyzers.
• Debug hardware, firmware, RTL, and system-level issues with cross-functional teams.
• Develop Python-based automation frameworks for test execution and data analysis.
• Document validation results and production readiness reports.

Skills

Post-silicon validation

DVT leadership

Python automation

Lab equipment expertise

High-speed protocols

Root-cause analysis

Cross-functional collaboration

Education

B.S./M.S. in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Oscilloscopes

BERTs

Protocol analyzers

Network analyzers

Logic analyzers

Job description

Celero Communications, Inc. in Irvine, CA is seeking an experienced Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs powering AI and hyperscale optical networking.

You will drive silicon characterization and readiness for production. As a technical leader, you will shape validation strategy, build infrastructure, and collaborate across Architecture, RTL, Firmware, Systems, and Customer Engineering.